Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 18/12/2025 01:12:40 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Memory Subsystem Design and Integration Engineer

your career. THE ROLE The Memory Subsystem team is seeking experienced RTL design engineers to contribute to the development... Excellent knowledge of System Verilog and Verilog language with respect to RTL design. Advanced DDR subsystem architecture...

Lugar: Austin, TX | 17/12/2025 23:12:12 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Physical IC Design Engineer

, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out..., and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth...

Lugar: San Jose, CA | 17/12/2025 22:12:11 PM | Salario: S/. No Especificado | Empresa: Broadcom