FPGA Engineer, LEO Payload FPGA

bitstreams. - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing... with uArchitecture, RTL coding, FPGA optimization for timing & power, simulation, and validation Preferred Qualifications...

Lugar: Redmond, WA | 19/12/2025 03:12:17 AM | Salario: S/. No Especificado | Empresa: Amazon

Senior Digital Design Engineer

logic required to implement new products in a wide range of application spaces RTL digital design and problem solving... such as linear regulators, DC-DC converters, data converters, and mixed signal processing functions. RTL design for synchronous...

Lugar: Chandler, AZ | 19/12/2025 02:12:21 AM | Salario: S/. No Especificado | Empresa: Analog Devices

Principal Electrical Engineer - ASIC/FPGA

and design using RTL, timing closure, verification, and system integration Recommend new tools and practices for continuous... experience or an Advanced Degree in a related field and minimum 5 years of experience RTL coding and simulation in VHDL...

Lugar: Cedar Rapids, IA | 19/12/2025 01:12:09 AM | Salario: S/. No Especificado | Empresa: Raytheon Technologies

Senior Circuit Design Engineer

clocking, and power management solutions. Drive the design and physical implementation of custom digital IPs from RTL..., etc..) is a plus. Experience with RTL, logic synthesis and verification is a plus. Mixed signal circuit design experience...

Lugar: Santa Clara, CA | 19/12/2025 00:12:50 AM | Salario: S/. No Especificado | Empresa: Nvidia

Senior/Principal ASIC Digital Design Engineer

, recurring cost and security functions. Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages... methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification...

Lugar: Boise, ID | 18/12/2025 23:12:04 PM | Salario: S/. No Especificado | Empresa: Idaho Scientific