of EDA tools-especially in areas like synthesis, RTL architecture, place and route and ECO methodologies-you are eager.... What You'll Need: Deep technical expertise in EDA tools, especially in synthesis, RTL architecture, place and route and ECO...
, simulation, and layout Digital RTL simulation, synthesis, & place-n-route tools Analog/RF measurement and digital capture...
, and interface functions that are protocol or standard compliant RTL implementation in SystemVerilog/Verilog of digital functions... Block-level verification including testbench creation, test plan definition, test case creation/debug, RTL and gate‑level...
Lugar:
Irvine, CA | 30/10/2026 00:10:06 AM | Salario: S/. $110000 - 165000 per year | Empresa:
MaxLinear, and security subsystems. Collaborate with RTL, verification, physical design, firmware, software, and systems teams throughout... knowledge of RTL development and verification methodologies. Experience with architecture modeling and performance analysis...
logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...
, from early architectural modeling through RTL implementation to silicon validation! In this role, you will work closely... with software, architecture, RTL, physical design, and validation teams to identify power-saving opportunities, guide key design...
requirements into hardware specifications, develop RTL using a hardware description language, create simulation-based testbenches... and verification skills while gaining experience in RTL development, functional verification, semiconductor design workflows...
Principal Physical Design Engineer Core Responsibilities RTL-to-GDSII Execution: Own physical implementation...
, verification, and layout teams to ensure accurate functionality, testability, and manufacturability Drive schematic‑level and RTL... digital datapath design (memory, SerDes, or SoC datapath). 2+ years of hands‑on experience with digital schematic build, RTL...
with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the...