GPU Design Verification Engineer

of our innovative graphics IP. By collaborating closely with architects, RTL developers, and physical design teams, your contributions...

Lugar: Folsom, CA | 29/10/2026 00:10:29 AM | Salario: S/. No Especificado | Empresa: Intel

FPGA IP Software Development Engineer

, and debugging FPGA-based systems for embedded, networking, and acceleration applications. This role is primarily focused on FPGA RTL..., and validate RTL for FPGA-based systems and platforms. Implement and integrate FPGA subsystems various I/0 Technologies (PCIe...

Lugar: San Jose, CA | 28/10/2026 23:10:18 PM | Salario: S/. No Especificado | Empresa: Altera

Design Verification Engineer, New Grad

, and recovery, and work with architects, RTL designers, and firmware engineers. About the Role As a new grad Design Verification... regressions, debug simulation failures, and work with RTL designers to find and fix bugs before tape-out. Responsibilities...

Lugar: San Jose, CA | 28/10/2026 20:10:33 PM | Salario: S/. $120000 - 150000 per year | Empresa: SambaNova

SOC Design Verification Engineer

, and verification or similarly for custom circuit design/layout flow. Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso...

Lugar: San Diego, CA | 28/10/2026 20:10:47 PM | Salario: S/. $101400 - 152200 per year | Empresa: Qualcomm

Physical Design Engineer, New Grad

and improve our RTL to GDS flow on advanced process nodes. You'll write TCL and Python scripts to automate flow steps, help... Understanding of the RTL to GDS flow, including synthesis and place and route Scripting experience in TCL, Perl, or Python...

Lugar: San Jose, CA | 28/10/2026 20:10:45 PM | Salario: S/. $120000 - 150000 per year | Empresa: SambaNova

Staff Digital IC Design Engineer

, and interface functions that are protocol or standard compliant RTL implementation in SystemVerilog/Verilog of digital functions... Block-level verification including testbench creation, test plan definition, test case creation/debug, RTL and gate-level...

Lugar: Irvine, CA | 28/10/2026 20:10:59 PM | Salario: S/. $110000 - 165000 per year | Empresa: MaxLinear

Chip Lead

, planning, dependencies, and risk mitigation. Collaborate across architecture, RTL, verification, physical design, validation... processes. PREFERRED EXPERIENCE Strong ASIC/SoC development experience across multiple areas, such as architecture, RTL...

Lugar: Santa Clara, CA | 28/10/2026 20:10:36 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices