Senior Architecture Modeling Engineer, AWS Machine Learning Accelerators
architecture, integration with other model or infrastructure components, testing, and debug - Work closely with architecture, RTL...
architecture, integration with other model or infrastructure components, testing, and debug - Work closely with architecture, RTL...
verification of RTL units for next generation chip designs. This will involve the candidate having deep knowledge of architectural... verification plan. Applying various FV techniques to proof correctness of digital designs. Debugging RTL to identify failure...
. Completes monthly Store Visit Form for review with RTL and optical team. Ensures all operating policies and procedures...
analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product... holes, chain failures, and pattern simulation issues Work with RTL and verification teams to ensure DFT requirements...
aspects of taking RTL to silicon tape-out. Key Responsibilities Full-Flow Implementation: Lead block-level and top-level...
more, and work quickly. Join us to power the future of the digital world. Your Impact RTL-to-GDSII implementation, including... efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT, Implementation, EDA...
, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor... of high-performance networking chips. You will: Drive RTL-to-GDSII implementation, including hierarchical floorplanning...
hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading... of architectural, functional, and performance issues. Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet...
and/or features The ideal candidate would have: 2+ year experience in FPGA or ASIC design from RTL/HDL through simulation...
and support of infrastructure tools used by design engineers for build and verification of architectural, RTL, and gate level...