Formal Verification Engineer - New College Grad 2027

verification of RTL units for next generation chip designs. This will involve the candidate having deep knowledge of architectural... verification plan. Applying various FV techniques to proof correctness of digital designs. Debugging RTL to identify failure...

Lugar: Santa Clara, CA | 28/10/2026 19:10:05 PM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia

ASIC DFT Engineer - Acacia (Hybrid)

analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product... holes, chain failures, and pattern simulation issues Work with RTL and verification teams to ensure DFT requirements...

Lugar: San Jose, CA | 28/10/2026 18:10:59 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Senior Physical Design Engineer

aspects of taking RTL to silicon tape-out. Key Responsibilities Full-Flow Implementation: Lead block-level and top-level...

Lugar: San Jose, CA | 28/10/2026 18:10:02 PM | Salario: S/. $121900 - 195000 per year | Empresa: Broadcom

Senior ASIC Physical Design Engineering Technical Lead

more, and work quickly. Join us to power the future of the digital world. Your Impact RTL-to-GDSII implementation, including... efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT, Implementation, EDA...

Lugar: San Jose, CA | 28/10/2026 18:10:00 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Physical Design Engineer

, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor... of high-performance networking chips. You will: Drive RTL-to-GDSII implementation, including hierarchical floorplanning...

Lugar: San Jose, CA | 28/10/2026 18:10:07 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

SR Design Verification Engineer

hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading... of architectural, functional, and performance issues. Root-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet...

Lugar: Santa Clara, CA | 28/10/2026 18:10:14 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices