Silicon Electrical Engineer

and silicon-based systems. Design, implement, and optimize RTL code using SystemVerilog and Verilog while ensuring performance..., or digital design development environments. Strong expertise in RTL design and development utilizing SystemVerilog and Verilog...

Lugar: San Francisco, CA | 28/10/2026 20:10:53 PM | Salario: S/. No Especificado | Empresa: Akkodis

Senior ASIC Physical Design Engineering Technical Lead

more, and work quickly. Join us to power the future of the digital world. Your Impact RTL-to-GDSII implementation, including... efficiency gaps and implementing incremental or transformative enhancements. Work closely with RTL, DFT, Implementation, EDA...

Lugar: San Jose, CA | 28/10/2026 18:10:58 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Formal Verification Engineer - New College Grad 2027

verification of RTL units for next generation chip designs. This will involve the candidate having deep knowledge of architectural... verification plan. Applying various FV techniques to proof correctness of digital designs. Debugging RTL to identify failure...

Lugar: Santa Clara, CA | 28/10/2026 18:10:44 PM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia

ASIC Physical Design Engineer

, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor... of high-performance networking chips. You will: Drive RTL-to-GDSII implementation, including hierarchical floorplanning...

Lugar: San Jose, CA | 28/10/2026 18:10:28 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Staff Digital IC Design Engineer

, and interface functions that are protocol or standard compliant RTL implementation in SystemVerilog/Verilog of digital functions... Block-level verification including testbench creation, test plan definition, test case creation/debug, RTL and gate-level...

Lugar: Irvine, CA | 28/10/2026 18:10:20 PM | Salario: S/. $110000 - 165000 per year | Empresa: MaxLinear

ASIC DFT Engineer - Acacia (Hybrid)

analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product... holes, chain failures, and pattern simulation issues Work with RTL and verification teams to ensure DFT requirements...

Lugar: San Jose, CA | 28/10/2026 18:10:57 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

GPU Design Verification Engineer

of our innovative graphics IP. By collaborating closely with architects, RTL developers, and physical design teams, your contributions...

Lugar: Folsom, CA | 28/10/2026 18:10:41 PM | Salario: S/. No Especificado | Empresa: Intel

Senior/Principal Physical Design Engineer (remote)

Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. You’ll.... Collaborate closely with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure...

Lugar: Denver, CO | 28/10/2026 03:10:36 AM | Salario: S/. No Especificado | Empresa: Chelsea Search Group