SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM - Write RTL... performance. Knowledge of Cache design/architecture Working knowledge of RTL modeling. Deep understanding of nanometer device...

Lugar: Santa Clara, CA | 05/04/2025 19:04:58 PM | Salario: S/. $117800 - 177900 per year | Empresa: Apple

ASIC Engineer

. · Experience with ASIC design (RTL coding, timing closure, etc.) Learn more about us right here: [1] [2] [3] [4] [5...

Lugar: San Jose, CA | 05/04/2025 17:04:24 PM | Salario: S/. $133300 - 186800 per year | Empresa: Cisco Systems

ASIC Verification Engineer

Design Verification Team, you will work with other verification, DSP, and RTL engineers to ensure successful verification...

Lugar: Maynard, MA | 05/04/2025 17:04:51 PM | Salario: S/. $118700 - 164700 per year | Empresa: Cisco Systems

SRAM Circuit Design Engineer

team to create optimal GDS. - Verify extracted GDS meets design specifications. - Backend verification, IR/EM. - Write RTL... and high performance. Knowledge of Cache design/architecture, memory hierarchy is a huge plus. Working knowledge of RTL...

Lugar: Austin, TX | 05/04/2025 17:04:37 PM | Salario: S/. No Especificado | Empresa: Apple