Full Chip Layout - Physical Architect

analysis etc. In-depth understanding on rtl to gds2 flow and understanding of basic device physics. Past experience... domains to Physical Design, viz., RTL, verification, DFx, post-Si etc. Exposure to various industry standard Physical Design...

Lugar: Santa Clara, CA | 20/03/2025 19:03:19 PM | Salario: S/. No Especificado | Empresa: Intel

PLL/Clocking Design Engineer

architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus. Attention to Detail: Exceptional...

Lugar: Beaverton, OR | 20/03/2025 19:03:36 PM | Salario: S/. No Especificado | Empresa: Apple

Intern, Digital Design - Summer 2025

driven execution. Roles & Responsibilities This position has responsibility for: Verilog/SV RTL Design: Create or modify... such as Python Coursework in digital design (RTL), design debug and digital verification (Verilog, SystemVerilog, VHDL) Coursework...

Lugar: Austin, TX | 20/03/2025 18:03:00 PM | Salario: S/. No Especificado | Empresa: Murata

Director, Team Manager

Expert Leader and RTL Program Leader) on the holistic leadership and approach to developing early and mid-career talent...

Lugar: Irving, TX | 20/03/2025 18:03:36 PM | Salario: S/. $116000 - 164000 per year | Empresa: Gartner

Sr Low Power Design Engineer

-functional teams to optimize power consumption at various stages of the design process, from RTL to synthesis and P&R. Key... at both RTL and physical design levels, including clock gating, power gating, multi-Vt optimization, and DVFS techniques...

Lugar: San Jose, CA | 20/03/2025 18:03:55 PM | Salario: S/. $155000 - 175000 per year | Empresa: Encore Semi

ASIC Verification Engineer

, developing and testing some of the most complex ASICs being developed in the industry. You will work with front-end RTL Design...

Lugar: San Jose, CA | 20/03/2025 18:03:00 PM | Salario: S/. $133300 - 186800 per year | Empresa: Cisco Systems

SoC Design Engineer

design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality Knowledge of high...

Lugar: Santa Clara, CA | 20/03/2025 18:03:32 PM | Salario: S/. $110600 - 135000 per year | Empresa: OmniVision

ASIC SoC Architect

for defense and commercial applications based on Idaho Scientific’s Helios secure RISC-V CPU. The RTL already exists – the major...-standard design methodologies to finalizing the RTL code, synthesis, place-and-route and verification. Be the primary...

Lugar: Boise, ID | 20/03/2025 02:03:11 AM | Salario: S/. No Especificado | Empresa: Idaho Scientific

Digital Design Engineer

, I/O, power consumption, area utilization, recurring cost and security functions. Implement and simulate IP blocks in RTL using... architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal...

Lugar: Boise, ID | 20/03/2025 02:03:16 AM | Salario: S/. No Especificado | Empresa: Idaho Scientific