to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...
augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...
test results. Other information: Must have and maintain RTL license in the state of Arkansas. Must have and maintain...
augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...
Name JBPHH-HIC RTL MAIN STR Salary Minimum $15.00 Salary Maximum $28.06...
design center (ODC) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification.../block-level test benches, executing verification plans, analysis/debugging RTL, and gate-level emulation failures...
signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC...
-architecture specifications. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support...
test environment. Debug test failures to determine the root cause;work with RTL, DV, emulation and post-Si engineers... and RTL code using simulation tools. Proficient in using UVM testbenches and working in Linux and Windows environments. SoC...
augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...