ASIC Physical Design Engineer

Perform PPA optimization with Fusion compiler to enhance ASIC efficiency. Conduct RTL and netlist level power analysis.... Setup, run, debug, and analyze reports of ASIC flows including Synthesis, PD, Power, and Timing. Implement blocks at RTL...

Lugar: San Francisco, CA | 28/03/2026 18:03:27 PM | Salario: S/. No Especificado | Empresa: Mercor

Firmware Engineer

and/or Verilog/SystemVerilog is essential for RTL (Register Transfer Level) design. FPGA Tools: Experience with industry-standard...

Lugar: Lexington, MA | 28/03/2026 03:03:26 AM | Salario: S/. $129000 - 171000 per year | Empresa: Anduril Industries