Vice President

development lifecycle — from architecture definition and RTL design through physical implementation, verification, and tape-out...

Lugar: New York City, NY | 22/05/2026 20:05:07 PM | Salario: S/. No Especificado | Empresa: Virtusa

Staff SoC Physical Verification Engineer, HBM

) optimization tools. Partner with physical design, custom layout, computer‑aided design (CAD), register‑transfer level (RTL... or customization. Working knowledge of full RTL‑to‑GDS implementation flows, including place‑and‑route, extraction, and their impact...

Lugar: Richardson, TX | 22/05/2026 19:05:10 PM | Salario: S/. No Especificado | Empresa: Micron

ASIC Design Engineer I, Satellite Communications

from system specification to chip specification to RTL to optimizing timing / power to chip level validation. · Drive high... and implementing Digital Signal Processing (DSP) algorithms and systems in RTL. - Ability to convert DSP algorithms into RTL code...

Lugar: San Diego, CA | 22/05/2026 19:05:02 PM | Salario: S/. No Especificado | Empresa: Amazon

Camera DE Lead Engineer

processing pipelines Design, implement, and own ASIC IP blocks, from architecture through RTL delivery Develop high‑quality RTL... across RTL development, review, debug, and verification workflows Identify, prototype, and drive measurably impactful GenAI...

Lugar: San Diego, CA | 22/05/2026 18:05:00 PM | Salario: S/. No Especificado | Empresa: Qualcomm

DFT architect / lead

transition from pre-silicon RTL to high-volume manufacturing (HVM). Your Job Architectural Leadership: Define and own the... time. Cross-Functional Integration: Lead the integration of DFT requirements into RTL, Synthesis, and Physical Design (STA...

Lugar: Texas | 22/05/2026 18:05:29 PM | Salario: S/. No Especificado | Empresa: GlobalFoundries

DSP Engineer

of DSP software. Hands-on experience with Software Defined Radios (SDRs) such as USRP, RTL-SDR, or similar hardware...

Lugar: Aberdeen, MD | 22/05/2026 17:05:52 PM | Salario: S/. No Especificado | Empresa: LufCo

Senior FPGA Design Engineer

knowledge about RTL design, FPGA prototyping and computer architecture. As the Senior FPGA Design Engineer for Axiado..., Verification, ASIC Design and Software teams, and report into the Engineering organization. Key Responsibilities RTL design...

Lugar: San Jose, CA | 22/05/2026 17:05:48 PM | Salario: S/. $150000 - 200000 per year | Empresa: Axiado