Senior ASIC Design Engineer

, or equivalent experience. 8+ years of build/RTL experience working on complex units in xbar/memory system. Highly proficient.... A deep understanding of ASIC flow including RTL, verification, logic synthesis, timing analysis, ECO, and post silicon debug...

Lugar: Santa Clara, CA | 21/05/2026 21:05:18 PM | Salario: S/. No Especificado | Empresa: Nvidia

FPGA Engineer (Space)

RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions Integrate and deploy... Verilog and/or VHDL Foundational knowledge of digital logic and timing considerations Experience with RTL design for various...

Lugar: Tempe, AZ | 21/05/2026 20:05:17 PM | Salario: S/. No Especificado | Empresa: Viasat

Senior Director Digital Design

success. You understand the difference between RTL that synthesizes cleanly and code that creates downstream timing problems...-nanosecond latency requirements, and reliable link training logic. You still review critical RTL because that is where decisions...

Lugar: Sunnyvale, CA | 21/05/2026 19:05:52 PM | Salario: S/. No Especificado | Empresa: Synopsys

CPU DV Infrastructure Engineer

General Summary: As a CPU DV Infrastructure Engineer specializing in DV methodology and RTL design verification support... and maintain flows, scripts and systems around the RTL and Verification development work cycle like RTL simulators, emulators...

Lugar: Austin, TX | 21/05/2026 17:05:36 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles

such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis Experience... in VHDL design for an aerospace environment or space application Proficient in FPGA design flow including items such as RTL...

Lugar: Virginia | 21/05/2026 17:05:11 PM | Salario: S/. $114000 - 171000 per year | Empresa: Northrop Grumman