Senior SoC Power Architect
(RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) to deliver outstanding power solutions...
Lugar: Santa Clara, CA | 20/11/2025 22:11:05 PM | Salario: S/. No Especificado | Empresa: Nvidia
SoC Design Engineer
Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis...
Lugar: Santa Clara, CA | 20/11/2025 21:11:00 PM | Salario: S/. $110600 - 140000 per year | Empresa: OmniVision
IP Integration Engineer
. Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC...: Experience with the Cadence Virtuoso design environment Experience or coursework with RTL languages (i.e SystemVerilog, Verilog...
Lugar: Fort Collins, CO | 20/11/2025 20:11:39 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom
Design Verification Engineer
industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL...
Lugar: San Jose, CA | 20/11/2025 18:11:56 PM | Salario: S/. No Especificado | Empresa: Broadcom
Sr. ASIC Design Engineer (Silicon Engineering)
, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate... in RTL implementation PREFERRED SKILLS AND EXPERIENCE: Ability to solve complex problems including clock domain...
Senior GPU Low Power Architect
and verticals. What you'll be doing: Invent and innovate low power architectural/RTL solutions and drive features and roadmaps... efficient design techniques is essential. Design experience with industry tools such as SystemVerilog RTL, UVM, Verdi, UPF...
Lugar: Santa Clara, CA | 20/11/2025 03:11:08 AM | Salario: S/. No Especificado | Empresa: Nvidia
Physical Design Engineer
experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required, Perl is a plus. - Good...
Lugar: San Jose, CA | 20/11/2025 03:11:35 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom
Chip Integration Engineer
successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network.... 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static...
Lugar: San Jose, CA | 20/11/2025 01:11:02 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom
Senior SRAM Circuit Design Engineer
and waveform debugging tools. Write RTL and perform verification against circuit What we need to see: MS in Electrical...
Lugar: Santa Clara, CA | 20/11/2025 01:11:04 AM | Salario: S/. No Especificado | Empresa: Nvidia
Senior Application Engineer - FPGA/ASIC (35946-TPEN)
will have hands-on experience with RTL design verification, UVM, SystemVerilog, and Verilog/VHDL for FPGA and SoC design, as well... and Simulink for FPGA, ASIC, and SoC design verification or hardware development. Proficiency in RTL design verification, UVM...
Lugar: Natick, MA | 20/11/2025 00:11:07 AM | Salario: S/. No Especificado | Empresa: MathWorks