Senior Staff Design Engineer - Memory Subsystem COE

customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.... What You Can Expect Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration...

Lugar: Santa Clara, CA | 15/05/2026 01:05:35 AM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell

EDA- CAD Engineer

, physical design, verification and familiarity with RTL/synthesis). Running and Debugging Physical Verification flows...

Lugar: San Jose, CA | 14/05/2026 23:05:38 PM | Salario: S/. $145800 - 194400 per year | Empresa: Western Digital

DV Lead

, and cross-functional collaboration skills, with close interaction across RTL, physical design, and post-silicon teams to ensure...

Lugar: Santa Clara County, CA | 14/05/2026 22:05:22 PM | Salario: S/. No Especificado | Empresa: MRL Consulting Group