RFIC Design Engineer
spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...
Lugar: Los Angeles, CA | 29/10/2025 03:10:20 AM | Salario: S/. No Especificado | Empresa: Apple
Electrical Engineer II - ASIC/FPGA Mission Systems (Onsite)
Implement ASIC / FPGA digital design using RTL Support verification and system integration of ASIC / FPGA implementations... is required prior to start date RTL coding and simulation in VHDL, Verilog, or SystemVerilog Experience with debugging and root...
Lugar: El Segundo, CA | 29/10/2025 03:10:03 AM | Salario: S/. $66000 - 130000 per year | Empresa: Raytheon Technologies
CPU Processor Power Management Verification Engineer
with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop...
Lugar: Santa Clara, CA | 29/10/2025 02:10:22 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple
CPU Design Verification Engineer
in a CPU design, you will have the responsibilities as follows: • Work closely with architecture and RTL designers on verifying...
Lugar: Austin, TX | 29/10/2025 02:10:11 AM | Salario: S/. No Especificado | Empresa: Apple
CPU Design Verification Engineer
responsibilities: • Work closely with architecture and RTL designers on verifying the functionality correctness of the design • Develop...
Lugar: Santa Clara, CA | 29/10/2025 02:10:22 AM | Salario: S/. No Especificado | Empresa: Apple
Senior Electrical Engineer - ASIC/FPGA Mission Systems (Onsite)
architecture and design using RTL, timing closure, verification, and system integration Recommend new tools and practices... and transferable SECRET U.S. government issued security clearance is required prior to start date. RTL coding and simulation in VHDL...
Lugar: El Segundo, CA | 29/10/2025 02:10:02 AM | Salario: S/. $82000 - 164000 per year | Empresa: Raytheon Technologies
SOC Verification Engineer
team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...
Lugar: San Francisco, CA | 29/10/2025 02:10:58 AM | Salario: S/. No Especificado | Empresa: Apple
Senior ASIC Design Engineer – Clocks IP
of timing closure to innovate and implement new Clocking topologies in RTL. Collaborate with Physical design and timing team..., we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. Get involved in end-to-end cycle...
Lugar: Santa Clara, CA | 29/10/2025 02:10:52 AM | Salario: S/. No Especificado | Empresa: Nvidia
WSoC PHY/MAC Validation and Integration Engineer
. Validate and characterize algorithms on real silicon alongside RTL, PHY, RF, MAC, and board designers. Bring-up...
Lugar: San Francisco, CA | 29/10/2025 01:10:18 AM | Salario: S/. $126800 - 190900 per year | Empresa: Apple
WSoC PHY/MAC Validation and Integration Engineer
. Validate and characterize algorithms on real silicon alongside RTL, PHY, RF, MAC, and board designers. Bring-up...
Lugar: San Francisco, CA | 29/10/2025 01:10:11 AM | Salario: S/. No Especificado | Empresa: Apple