FPGA Developer
tools, such as AMD Vitis or Intel Quartus Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa...
Lugar: Beavercreek, OH | 08/05/2026 01:05:04 AM | Salario: S/. No Especificado | Empresa: Booz Allen Hamilton
Lead Performance Modeling Architect, CPU Fabric and LLC
data-driven decision-making. Act as the primary liaison between Architecture, RTL Build, and Software teams to resolve... accuracy against RTL or silicon and the ability to explain complex performance "cliffs" to executive collaborators. Ways...
Lugar: Santa Clara, CA | 08/05/2026 00:05:02 AM | Salario: S/. No Especificado | Empresa: Nvidia
Senior Digital Design Engineer
and performance requirements. (Verilog/SystemVerilog). Complete high-quality, area-optimal, low-power RTL design using industry..., RTL coding, FPGA, Computer Architecture, Digital Verification. Minimum 3 years of experience in similar role of Digital...
Lugar: Chandler, AZ | 08/05/2026 00:05:52 AM | Salario: S/. No Especificado | Empresa: NXP Semiconductors
ASIC Design Engineer - New College Grad 2026
, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis and timing...
Lugar: Santa Clara, CA | 07/05/2026 23:05:41 PM | Salario: S/. $100000 - 166750 per year | Empresa: Nvidia
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects... teams to develop high-quality SDC constraints Drive RTL-to-netlist activities including synthesis, logical equivalence...
Lugar: North Reading, MA | 07/05/2026 23:05:39 PM | Salario: S/. $192300 per year | Empresa: Teradyne
Design Verification Engineer (Data Fabric Verification Engineer)
verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes. Exposure to RTL design... of the design. Coordinate with RTL engineers to implement logic design for better clock gating and verify the various...
Lugar: Austin, TX | 07/05/2026 23:05:10 PM | Salario: S/. $45000 - 121000 per year | Empresa: Wipro
Sr. ASIC Design Engineer
and timing closure. You will identify and fix timing in RTL to meet the frequency target. Work with the Verification team...
Lugar: Roseville, CA | 07/05/2026 22:05:59 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
Senior Staff Design Verification Engineer – Memory Sub-System (DDR/LPDDR/HBM )
customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation...
Lugar: Santa Clara, CA | 07/05/2026 21:05:26 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell
Senior ASIC Program Manager
: architecture, RTL, design verification, physical design, tape-out, silicon bring-up, validation, and production release Own... across engineering disciplines: RTL, DV, physical design, DFT, CAD, test, packaging, product engineering, systems, and firmware Lead...
Lugar: Sunnyvale, CA | 07/05/2026 20:05:45 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise
Senior Staff Design Verification Engineer – Memory Sub-System
customers — working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation...
Lugar: Santa Clara, CA | 07/05/2026 18:05:37 PM | Salario: S/. $134390 - 201300 per year | Empresa: Marvell