Senior Applications Engineer - Emulation

: Experience with an Emulation platform (Veloce, Palladium, Zebu) is preferred SystemVerilog, Verilog and/or VHDL RTL design... of RTL designs and simulation Proficient in scripting languages (e.g., Perl, Python, various shell scripts/Makefiles, XML...

Lugar: Austin, TX | 28/04/2026 22:04:11 PM | Salario: S/. No Especificado | Empresa: Siemens

Principal Engineer

on all levels of ASIC development, spanning high-level architecture, to RTL design and verification and volume manufacturing... your knowledge of specifications, mathematics, and computation to write efficient and elegant RTL for implementing components...

Lugar: San Jose, CA | 28/04/2026 20:04:25 PM | Salario: S/. No Especificado | Empresa: Broadcom

IC Design Engineer

Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power-intent...

Lugar: San Jose, CA | 28/04/2026 20:04:43 PM | Salario: S/. No Especificado | Empresa: Broadcom

Senior Software Development Engineer

development for RX equalization, DFE/FFE adaptation, eye monitoring of Serdes IPs Must have experience with pre-silicon/RTL...

Lugar: USA | 28/04/2026 19:04:28 PM | Salario: S/. $108000 - 172800 per year | Empresa: Broadcom

Front-End Infrastructure Engineer

-quality support for verification processes. RTL Architecture Tool Deployment & Support: You will successfully deploy... and maintain tools for RTL Architecture, ensuring integration with FE verification flows and addressing any support requirements...

Lugar: Austin, TX | 28/04/2026 17:04:47 PM | Salario: S/. No Especificado | Empresa: Protingent

Senior FPGA Engineer

challenges affecting PCB layouts to ensure robustness. Develop synthesizable RTL code using Verilog or VHDL, create test benches.... Expertise in HDL programming (Verilog and/or VHDL) for synthesizable RTL and verification. Experience with FPGAs and SoCs...

Lugar: Pleasanton, CA | 27/04/2026 17:04:36 PM | Salario: S/. $130000 - 155000 per year | Empresa: Vector Atomic

Staff FPGA Engineer

challenges affecting PCB layouts to ensure robustness. Develop synthesizable RTL code using Verilog or VHDL, create test benches.... Expertise in HDL programming (Verilog and/or VHDL) for synthesizable RTL and verification. Experience with FPGAs with AMD Zynq...

Lugar: Pleasanton, CA | 27/04/2026 17:04:27 PM | Salario: S/. $150000 - 180000 per year | Empresa: Vector Atomic