Senior Applications Engineer – DDR Design IP

, marketing and R&D teams to win opportunities Run Verilog simulations to enable IP benchmarking Run RTL synthesis for area... Experience on memory subsystem verification and/or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog...

Lugar: San Jose, CA | 10/10/2025 18:10:36 PM | Salario: S/. $84000 - 156000 per year | Empresa: Cadence Design Systems

Senior Circuit Design Engineer

the design and physical implementation of custom digital IPs from RTL to layout using industry standard tools and custom... circuits (power gating, decaps, multi-vt, etc..) is a plus. Experience with RTL, logic synthesis and verification...

Lugar: Santa Clara, CA | 10/10/2025 18:10:17 PM | Salario: S/. No Especificado | Empresa: Nvidia

Design Engineer Intern

Additional Desirable Skills: Having experience with Verilog RTL coding design. The Salary Range for this position is $29...

Lugar: Newport Beach, CA | 10/10/2025 02:10:07 AM | Salario: S/. $29 - 34 per hour | Empresa: MACOM

RFIC Layout Engineer

spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation...

Lugar: Irvine, CA | 10/10/2025 02:10:26 AM | Salario: S/. $42.23 - 75.14 per hour | Empresa: Apple

Intern - System Engineer, HBM

. Experience with RTL modeling using Verilog or SystemVerilog. Hands-on experience programming and debugging FPGAs...

Lugar: Boise, ID | 09/10/2025 23:10:07 PM | Salario: S/. No Especificado | Empresa: Micron

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... design experience in: o memory system development o RTL/micro-architecture definition o PPA (performance/power/area...

Lugar: Santa Clara, CA | 09/10/2025 22:10:37 PM | Salario: S/. No Especificado | Empresa: Apple

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... subsystem Academic experience with RTL/micro-architecture development Good understanding of PPA (performance/power/area...

Lugar: Santa Clara, CA | 09/10/2025 21:10:29 PM | Salario: S/. $126800 - 190900 per year | Empresa: Apple

SoC Design/Integration & Synthesis Engineer

design, writing UPFs, close on power intent verification at the chip level. - Work on RTL integration, timing constraints... with scripting languages like Perl or Tcl or Python RTL logic design or implementation experience on multi-million gate ASICs...

Lugar: Cupertino, CA | 09/10/2025 20:10:58 PM | Salario: S/. No Especificado | Empresa: Apple

Principal Digital IC Design Engineer

Engineer within Custom Silicon Engineering (CCS), you will be part of a high-performance RTL team responsible for architecting... and implementing advanced SoC designs. CCS serves as the core execution engine for customer-driven silicon programs, delivering RTL, DV...

Lugar: Santa Clara, CA | 09/10/2025 19:10:07 PM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell