STA Engineer

) Strong understanding of ASIC design flows, including RTL and place-and-route. Excellent problem-solving skills and attention to detail...

Lugar: San Jose, CA | 09/10/2025 18:10:09 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

ASIC Design Engineer - Cache Controller

trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design... design experience in: o memory system development o RTL/micro-architecture definition o PPA (performance/power/area...

Lugar: Santa Clara, CA | 09/10/2025 17:10:43 PM | Salario: S/. No Especificado | Empresa: Apple

MTS Digital Engineering

for new product development Responsible for RTL coding, functional simulation, analog-block Verilog model, post-pr simulation...

Lugar: San Jose, CA | 09/10/2025 02:10:50 AM | Salario: S/. $93000 - 172000 per year | Empresa: Rambus

CPU CAD Design Automation Engineer

. You will be responsible for: Develop and to architect new tools and flows for RTL to physical design as well as enhance existing flows... for better efficiency and robustness. Develop and maintain RTL to layout design infra-structure, including full internal cloud management...

Lugar: Austin, TX | 08/10/2025 22:10:45 PM | Salario: S/. No Especificado | Empresa: Intel

Camera DV Engineer

Random stimulus Strong Digital Design concepts and debugging skills with expertise in traversing Verilog/System-Verilog RTL...

Lugar: San Diego, CA | 07/10/2025 23:10:07 PM | Salario: S/. No Especificado | Empresa: Qualcomm

GenAI Physical Synthesis Engineer

our RTL-to-GDS implementation flows. You will be directly responsible for creating AI-powered agents using technologies...

Lugar: Austin, TX | 07/10/2025 22:10:59 PM | Salario: S/. No Especificado | Empresa: Apple

Digital IC Design Staff Engineer

design and application-specific integrated circuit (ASIC) design flows. Perform RTL coding and functional verification... following skill sets gained during professional or academic experience: RTL design, Verilog and/or SystemVerilog;Synthesis...

Lugar: Santa Clara, CA | 07/10/2025 21:10:06 PM | Salario: S/. $105470 - 158000 per year | Empresa: Marvell

Senior ASIC Physical Design Engineer, Netlisting

. Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools. Deep understanding... of hardware architecture and hands-on skills in RTL/logic design for timing closure. Experience in clock-domain-crossing...

Lugar: Santa Clara, CA | 07/10/2025 20:10:01 PM | Salario: S/. No Especificado | Empresa: Nvidia