infrastructure, automate PD flows, improve CAD infrastructure Collaborate with RTL Designers and provide Physical Design feedback..., and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on advanced...
Lugar:
Austin, TX | 16/04/2026 22:04:21 PM | Salario: S/. $15000 - 27000 per year | Empresa:
Etched: Design and implement digital subsystems and IP blocks for mixed-signal ICs from architecture through tape-out. Develop RTL... knowledge of Verilog RTL design. Solid understanding of the digital design flow, including: Microarchitecture and RTL...
Lugar:
USA | 16/04/2026 22:04:30 PM | Salario: S/. No Especificado | Empresa:
Cirrus Logic, with a focus on applying AI/ML to improve design productivity, quality, and scalability. Key Responsibilities Lead RTL digital... and Experience Expertise in digital circuit design and RTL development (Verilog/SystemVerilog) Strong understanding of complete...
with minimal direction. You collaborate naturally with cross-functional teams — from RTL design to software and emulation...
Lugar:
Austin, TX | 16/04/2026 20:04:56 PM | Salario: S/. $15000 - 27000 per year | Empresa:
Etched timing constraints for intricate SoC designs. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the..., from RTL to GDSII. Knowledge and hands-on experience with sta methodologies and implementation. Proficiency in using STA...
Lugar:
Irvine, CA | 16/04/2026 19:04:16 PM | Salario: S/. $135900 - 201130 per year | Empresa:
Marvell. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities.... Strong understanding of ASIC design flows, from RTL to GDSII. Knowledge and hands-on experience with synthesis and STA methodologies...
Lugar:
Irvine, CA | 16/04/2026 19:04:46 PM | Salario: S/. $135900 - 201130 per year | Empresa:
Marvell future of the FPGA industry. About the Role Join Altera as an FPGA Silicon Design Engineer focused on RTL design.... In this role, you will be responsible for developing high-quality logic designs and RTL implementations for next-generation FPGA...
Lugar:
San Jose, CA | 16/04/2026 19:04:36 PM | Salario: S/. No Especificado | Empresa:
Altera, power, cost, and schedule. Build RTL using VHDL/Verilog and drive synthesis, place and route, and timing closure...
: Design and implement digital subsystems and IP blocks for mixed-signal ICs from architecture through tape-out. Develop RTL... knowledge of Verilog RTL design. Solid understanding of the digital design flow, including: Microarchitecture and RTL...
Lugar:
USA | 16/04/2026 17:04:49 PM | Salario: S/. No Especificado | Empresa:
Cirrus Logic, Perl) Prior RTL design flow experience in DRAM or Foundry processes. Job Profile(s): Systems Design Engineer 2...