Senior ASIC DV Engineer
metrics from specifications and writing block and chip-level tests. Debugging RTL and Gate simulations and work with design...
Lugar: San Jose, CA | 16/04/2026 17:04:02 PM | Salario: S/. No Especificado | Empresa: Broadcom
Digital Design Engineer
: Design and implement digital subsystems and IP blocks for mixed-signal ICs from architecture through tape-out. Develop RTL... design experience. Master's with 0+ years of relevant experience. Strong working knowledge of Verilog RTL design. Solid...
Lugar: USA | 16/04/2026 17:04:22 PM | Salario: S/. No Especificado | Empresa: Cirrus Logic
Principal FPGA/ASIC Engineer - Level 3
Proficiency in FPGA design flow including items such as RTL/gate level simulation, synthesis, place & route, static timing...
Lugar: USA | 16/04/2026 17:04:49 PM | Salario: S/. $79300 - 118900 per year | Empresa: Northrop Grumman
Engineer, Digital Design Engineering
for routing video data Write block specifications and track execution at block and top level Use Verilog/SystemVerilog RTL...
Lugar: Centennial, CO - Colorado Springs, CO | 15/04/2026 21:04:09 PM | Salario: S/. $88236 - 121325 per year | Empresa: Analog Devices
Senior Consultant (Source Code Review)
++, RTL (Verilog/SystemVerilog), and processor/SoC architecture analysis to support IP litigation, infringement analysis... codebases, including firmware, device drivers, and kernel-level C/C++. Review and interpret RTL (Verilog/SystemVerilog...
Lugar: Austin, TX | 15/04/2026 17:04:32 PM | Salario: S/. No Especificado | Empresa: Lumenci
Software Engineering Manager (Client Platform)
, and workflows that power localization, internationalization (i18n), and right-to-left (RTL) support, expanding WHOOP's reach.... RESPONSIBILITIES: Own the execution and delivery of the Translations Platform roadmap, including RTL support, localization...
Lugar: Boston, MA | 15/04/2026 17:04:37 PM | Salario: S/. No Especificado | Empresa: Whoop
Physical Design Engineer II (Silicon Engineering)
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
Mixed Signal IP - Senior Program Manager
and RTL) to GDS MSEE preferred Key competencies critical thinking and problem-solving skills team work...
Lugar: USA | 15/04/2026 02:04:35 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
R&D Engineering, Sr Staff Engineer
RTL design, logic synthesis, and timing constraints (SDC authoring/debugging). Solid understanding of digital design...
Lugar: Hillsboro, OR | 14/04/2026 23:04:21 PM | Salario: S/. No Especificado | Empresa: Synopsys
Senior Principal Electrical Engineer (Hybrid)
. What You Will Do : ASIC/FPGA/SoPC digital architecture development and design. Develop RTL design code and simulation in VHDL, Verilog... years prior relevant experience or an Advanced Degree in a related field Proficient writing RTL and/or testbenches using...
Lugar: Cedar Rapids, IA | 14/04/2026 22:04:03 PM | Salario: S/. No Especificado | Empresa: Raytheon Technologies