Senior Engineer, Front End Computer Aided Design

Compile. - Expertise in RTL power/UPF linting flows like Power Artist/Jules, VCLP. - Expertise in RTL filelist generation, SoC... handling. - Design release packaging and qualification, RTL quality flows, static checks....

Lugar: Mountain View, CA | 10/12/2025 03:12:21 AM | Salario: S/. No Especificado | Empresa: Microsoft

Senior SOC Design Engineer

actionable improvements Ensure high-quality RTL delivery to the physical design team with thorough design quality checks... Expertise in RTL design, SOC integration, and design automation flows Proficiency in Perl, Python, or similar scripting...

Lugar: Santa Clara, CA | 10/12/2025 03:12:34 AM | Salario: S/. No Especificado | Empresa: Nvidia

Principal ML Architect

with computer architecture,Hardware/Software co-design, RTL Design and DV 6+ years of experience with architecture modeling...

Lugar: Mountain View, CA | 10/12/2025 02:12:20 AM | Salario: S/. No Especificado | Empresa: Microsoft

Physical Design Engineer (Req #KD-20260118)

to grow your career! \n Duties Responsible for all aspects of physical implementation from RTL to GDS, including RTL... foregoing fields plus six years of relevant experience is acceptable. In all cases, the position also requires knowledge of RTL...

Lugar: Austin, TX | 10/12/2025 02:12:11 AM | Salario: S/. No Especificado | Empresa: Cirrus Logic

Product Owner

:** 17839 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...

Lugar: Jacksonville, FL | 10/12/2025 02:12:15 AM | Salario: S/. $100000 - 118000 per year | Empresa: Acosta

Principal Design Engineer

will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis... specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure. 8+ years of experience...

Lugar: Mountain View, CA | 10/12/2025 01:12:28 AM | Salario: S/. No Especificado | Empresa: Microsoft

Senior ASIC Design Engineer

limitations. You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean... and development. Experience in micro-architecture and RTL development of complex designs in Verilog. Exposure to Digital systems...

Lugar: Santa Clara, CA | 10/12/2025 00:12:47 AM | Salario: S/. No Especificado | Empresa: Nvidia

Senior Design Engineer

, Register Transfer Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different subsystems... specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/LINT closure. 4+ years of experience...

Lugar: Mountain View, CA | 09/12/2025 22:12:29 PM | Salario: S/. No Especificado | Empresa: Microsoft