Sr. Silicon Design Verification Engineer

Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify Full-Chip...), Jasper and Synopsys (Magellan / VC Formal) is a plus. Experience with gate-level simulation, power-aware verification, reset...

Lugar: San Jose, CA | 15/10/2024 19:10:57 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

RTL Design Engineer

SystemVerilog Language · EDA tools Cadence and Synopsys · Strong communication and collaboration skills · Experienced...

Lugar: San Francisco, CA | 12/10/2024 17:10:46 PM | Salario: S/. No Especificado | Empresa: Capgemini

Research Engineer

. Experience in modeling semiconductor device for high voltage power electronic systems, using Synopsys SABER or similar..., Synopsys SABER, SPICE, Fusion 360, Altium, KiCAD Adept with laboratory equipment such as oscilloscopes, probes, LCR meter...

Lugar: Dearborn, MI | 11/10/2024 02:10:04 AM | Salario: S/. No Especificado | Empresa: Ford

Research Engineer

semiconductor device for high voltage power electronic systems, using Synopsys SABER or similar. Ability to replicate device slew..., Synopsys SABER, SPICE, Fusion 360, Altium, KiCAD Adept with laboratory equipment such as oscilloscopes, probes, LCR meter...

Lugar: Dearborn, MI | 10/10/2024 18:10:35 PM | Salario: S/. No Especificado | Empresa: Ford