FPGA/ASIC Design Engineer (Secret Clearance) - Camden, NJ
Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain...
Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain...
, Checkmarx, Corellium, Synopsys, Acunetix, VeraCode, SAST & DAST Tools, Plextrac, Cloud security (AWS / Azure / Oracle), Postman...
, Checkmarx, Corellium, Synopsys, Acunetix, VeraCode, SAST & DAST Tools, Plextrac, Cloud security (AWS / Azure / Oracle), Postman...
, Checkmarx, Corellium, Synopsys, Acunetix, VeraCode, SAST & DAST Tools, Plextrac, Cloud security (AWS / Azure / Oracle), Postman...
, Checkmarx, Corellium, Synopsys, Acunetix, VeraCode, SAST & DAST Tools, Plextrac, Cloud security (AWS / Azure / Oracle), Postman...
with software packages developed by EDA vendors (Synopsys, Siemens, Brion, Cadence, etc.), preferably in the areas of assist feature...
-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA... is a must Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado Strong logic/board debug, and analytical skills. Experience...
Implement Hierarchical blocks of the DDR/system cache subsystem running the physical synthesis with Synopsys Fusion Compiler... around obstacles. Proficient in running Physical synthesis with Synopsys Fusion Compiler on SoC Top Level blocks with complex power...
such as Synopsys VCS, Cadence Xcelium, Spyglass or equivalent Familiarity with at least one procedural programming language (C, C...
is a plus. Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC...