Power Engineer

Contract Worker for RTL Design and Verification with expertise in power profiling and automation. The ideal candidate will play.... Candidates will build run-time power models using Machine Learning techniques. Key Responsibilities: RTL Design...

Lugar: Sunnyvale, CA | 07/12/2025 01:12:55 AM | Salario: S/. $80000 - 158000 per year | Empresa: Wipro

FPGA Design Verification Engineer

, System Verilog, RTL). · Write and debug test cases to verify functionality, performance, and corner cases. · Identify... functions may be required. What you need: · Strong understanding of FPGA, ASIC, RTL design principles and architectures...

Lugar: Mountain View, CA | 07/12/2025 00:12:15 AM | Salario: S/. No Especificado | Empresa: UST

Physical Design SoC Clock Engineer

Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS...-on experience across the entire spectrum of RTL to GDS implementation on advance semiconductor technology nodes and specific...

Lugar: USA | 06/12/2025 22:12:20 PM | Salario: S/. No Especificado | Empresa: Intel

Logic Design Engineer

designs with scalabilities and flexibilities. Power and Area efficient RTL logic design and DV support. Running tools... and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests...

Lugar: USA | 06/12/2025 01:12:12 AM | Salario: S/. No Especificado | Empresa: Intel

Senior Staff Engineer, Physical Design

across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...

Lugar: Morrisville, NC | 06/12/2025 00:12:30 AM | Salario: S/. $125900 - 186260 per year | Empresa: Marvell

HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff

will have hands-on experience in RTL-to-GDSII flow, with a strong focus on Floor-planning, Clock Tree Synthesis, Place-n-Route (PnR... and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...

Lugar: Boulder, CO | 06/12/2025 00:12:09 AM | Salario: S/. $126000 - 189000 per year | Empresa: Qualcomm

Physical Design Engineer

datapath and interconnect solutions for next-generation AI accelerators. You'll work closely with RTL designers to define... implementation of floorplan blocks from floorplanning to final signoff Collaborate with RTL designers to drive optimal block...

Lugar: San Francisco, CA | 06/12/2025 00:12:48 AM | Salario: S/. No Especificado | Empresa: OpenAI