Digital/FPGA Engineer Lead - Space

. The day-to-day Own the architecture, design, and implementation of FPGA-based digital systems Develop RTL in Verilog... Strong experience with Verilog, SystemVerilog, or VHDL Experience across multiple stages of FPGA development: architecture, RTL design...

Lugar: Tempe, AZ | 28/03/2026 20:03:44 PM | Salario: S/. No Especificado | Empresa: Viasat

Digital Design Engineer (MPU)

RTL, verification, and silicon delivery. If you enjoy building processors, working close to the hardware, and solving... microarchitecture designs Design and implement digital modules using RTL Develop and integrate processor cores including RISC-V-based...

Lugar: Laguna Hills, CA | 28/03/2026 20:03:58 PM | Salario: S/. No Especificado | Empresa: BrainChip, Inc.

Lead ASIC DFT Engineer

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: San Jose, CA | 28/03/2026 19:03:41 PM | Salario: S/. No Especificado | Empresa: Cyient

Senior ASIC Synthesis and STA Engineer

verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages Validate clock... with RTL design principles and hardware description languages Ability to work effectively within multidisciplinary...

Lugar: Atlanta, GA | 28/03/2026 19:03:39 PM | Salario: S/. $119900 - 191500 per year | Empresa: Ciena

Digital ASIC Prototyping Engineer

by your peers and architects You are accountable for the creation and integration of ASIC RTL source code, algorithms and functions...

Lugar: Atlanta, GA | 28/03/2026 19:03:03 PM | Salario: S/. $119900 - 191500 per year | Empresa: Ciena