Principal Product Engineer

of digital IC/FPGA design from RTL to gate-level (Verilog/VHDL) Automation/scripting (e.g., Python, Perl, various shell scripts...

Lugar: Fremont, CA | 11/12/2025 23:12:41 PM | Salario: S/. No Especificado | Empresa: Siemens

Product Engineer - Tessent DFT

a plus: RTL coding and verification using Verilog/SystemVerilog/VHDL Synthesis and timing analysis Place and route Advanced IC...

Lugar: Santa Clara, CA | 11/12/2025 23:12:44 PM | Salario: S/. $129600 - 233300 per year | Empresa: Siemens

Product Engineer

skills. · RTL familiarity (Verilog/SystemVerilog/VHDL) and experience with synthesis, place & route, and FPGA tool flows...

Lugar: Fremont, CA | 11/12/2025 19:12:43 PM | Salario: S/. $129600 - 233300 per year | Empresa: Siemens