Graphics FE Integration Engineer

. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural..., you will be responsible for: - RTL integration, partitioning, design analysis and qualification. - Run logic equivalence checking...

Lugar: Santa Clara, CA | 15/01/2025 18:01:03 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

SoC Chiplet Design Lead

to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...

Lugar: Austin, TX | 15/01/2025 03:01:54 AM | Salario: S/. No Especificado | Empresa: SkillTorch

SoC Chiplet Design Lead

to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...

Lugar: Boston, MA | 15/01/2025 02:01:01 AM | Salario: S/. No Especificado | Empresa: SkillTorch

Senior Physical Design Engineer

augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...

Lugar: San Jose, CA | 15/01/2025 01:01:58 AM | Salario: S/. No Especificado | Empresa: Prodapt

ASIC Timing Engineer, Staff

signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC...

Lugar: San Diego, CA | 15/01/2025 01:01:42 AM | Salario: S/. No Especificado | Empresa: Qualcomm

SoC Chiplet Design Lead

to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...

Lugar: Santa Clara, CA | 14/01/2025 23:01:20 PM | Salario: S/. No Especificado | Empresa: SkillTorch

Senior Staff Emulation Engineer - ZEBU

design center (ODC) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification.../block-level test benches, executing verification plans, analysis/debugging RTL, and gate-level emulation failures...

Lugar: San Jose, CA | 14/01/2025 23:01:10 PM | Salario: S/. No Especificado | Empresa: Prodapt