Senior Digital Engineer

. Designing digital RTL that meets timing, area, power and any adhering standards specifications. Integrating design at the top...-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P...

Lugar: Chandler, AZ | 23/10/2026 17:10:32 PM | Salario: S/. No Especificado | Empresa: Renesas Electronics

Mgr III, ASIC - AMZ25936.5

with architecture, RTL design, software, and machine learning teams to ensure full coverage of functional requirements and performance...

Lugar: Cupertino, CA | 23/10/2026 17:10:34 PM | Salario: S/. No Especificado | Empresa: Amazon

Staff Applications Engineer, Synthesis and Formal Verification

ingenuity of tomorrow. You Are You have spent years in the trenches of ASIC design, and you know that the cleanest RTL... everything, and what you recommend will show up in silicon. What You'll Be Doing Own technical relationships with customer RTL, synthesis, formal...

Lugar: Sunnyvale, CA | 23/10/2026 17:10:40 PM | Salario: S/. $129000 - 193000 per year | Empresa: Synopsys

FPGA Engineer

, and deployment of FPGA-based products. This position is open to candidates with 7-10 years of experience, focusing on RTL design...-based products with a focus on RTL design, FPGA development, and simulation. Collaborate with hardware, embedded software...

Lugar: Newtown, PA | 23/10/2026 02:10:26 AM | Salario: S/. $55 - 67 per hour | Empresa: Actalent

CPU Cache Architect

experience in architecting processors, caches, and interconnect. Familiarity with Digital RTL Design, Software Development..., Verilog HDL. Experience writing and debugging RTL. Experience collaborating effectively towards the success of a project...

Lugar: Fort Collins, CO | 23/10/2026 01:10:59 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices