. Designing digital RTL that meets timing, area, power and any adhering standards specifications. Integrating design at the top...-architecture, Design partitioning, RTL Verilog / SystemVerilog Design, Generating Timing Constraints, Synthesis, Interaction with P...
-performance, area and power-efficient RTL designs to meet project specifications and targets Conduct in-depth analysis..., and area requirements Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean...
Lugar:
Austin, TX | 23/10/2026 17:10:08 PM | Salario: S/. No Especificado | Empresa:
Amazon proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving... or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs - Experience...
Lugar:
Austin, TX | 23/10/2026 17:10:37 PM | Salario: S/. No Especificado | Empresa:
Amazon with scripting (e.g., Python, Bash) and RTL design/verification (e.g., Verilog, SystemVerilog) for hardware security solutions...
ingenuity of tomorrow. You Are You have spent years in the trenches of ASIC design, and you know that the cleanest RTL... everything, and what you recommend will show up in silicon. What You'll Be Doing Own technical relationships with customer RTL, synthesis, formal...
Lugar:
Sunnyvale, CA | 23/10/2026 17:10:31 PM | Salario: S/. $129000 - 193000 per year | Empresa:
Synopsys, and deployment of FPGA-based products. This position is open to candidates with 7-10 years of experience, focusing on RTL design...-based products with a focus on RTL design, FPGA development, and simulation. Collaborate with hardware, embedded software...
Lugar:
Newtown, PA | 23/10/2026 01:10:43 AM | Salario: S/. $55 - 67 per hour | Empresa:
Actalent and Integration of various functional block RTL related to SOC clock controllers Perform design quality checks such as Timing closure.... Minimum 2+ year logic design experience Knowledge of logic design flow including Low Power Analysis, UPF, RTL coding...
, you will: Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal... in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place...
/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks...
Lugar:
San Diego, CA | 22/10/2026 22:10:36 PM | Salario: S/. $109000 - 164000 per year | Empresa:
UST. You collaborate naturally with cross-functional teams - from RTL design to software and emulation - and can clearly communicate...