Design Verification Engineer (Silicon Engineering)
with scripting languages, e.g. Python for automation RTL design, chip bring-up, and post-silicon validation experience Ability...
Sr. ASIC Design Verification Engineer (Silicon Engineering)
coverage models, and analyzing results Experience with scripting languages, e.g. Python for automation RTL design, chip bring...
Digital Verification Engineer I
or wireless modem architectures. Prior internship or project experience related to verification, RTL development...
Lugar: Austin, TX | 22/05/2026 01:05:05 AM | Salario: S/. $84000 - 156000 per year | Empresa: Silicon Labs
SystemC Modeling Developer
. · Validate models against RTL or hardware references to ensure functionality and accuracy. · Work with simulators... bring-up using virtual models. · Knowledge of RTL design (SystemVerilog) or hardware emulation (optional). · Experience...
Lugar: Redmond, WA | 22/05/2026 01:05:07 AM | Salario: S/. $80000 - 120000 per year | Empresa: UST
Firmware Engineering Lead
at Mercury is considered as Register-Transfer Level (RTL) or programmable logic. Job Responsibilities: Lead firmware...
Lugar: Cypress, CA | 22/05/2026 01:05:43 AM | Salario: S/. No Especificado | Empresa: Mercury Systems
Principal Hardware Design Engineer
and implement changes to improve yields Participate in a cross-functional team environment including Mechanical, RTL, and Software...
Lugar: Austin, TX | 22/05/2026 01:05:56 AM | Salario: S/. No Especificado | Empresa: Keysight Technologies
RTL2GDS, Senior Principal Design Engineer
block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery... Wireless and Mobile Customers Senior level Design Engineer position supporting RTL-to-GDS implementation flows using...
Lugar: Austin, TX | 21/05/2026 23:05:07 PM | Salario: S/. No Especificado | Empresa: Cadence Design Systems
CPU Design Verification Engineer
correctness and performance of Intel's ATOM processor family. Working alongside world-class CPU architects, RTL designers... Collaborate for Maximum Impact Partner closely with CPU architects, RTL developers, and physical design teams to verify complex...
Lugar: Austin, TX | 21/05/2026 23:05:50 PM | Salario: S/. $122440 - 172860 per year | Empresa: Intel
Senior Director Digital Design
success. You understand the difference between RTL that synthesizes cleanly and code that creates downstream timing problems...-nanosecond latency requirements, and reliable link training logic. You still review critical RTL because that is where decisions...
Lugar: Sunnyvale, CA | 21/05/2026 23:05:50 PM | Salario: S/. No Especificado | Empresa: Synopsys
FPGA Engineer (Space)
RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions Integrate and deploy... Verilog and/or VHDL Foundational knowledge of digital logic and timing considerations Experience with RTL design for various...