solve real time problems (e.g. software tool & IP issues, Design Closure, RTL and simulation assistance, system bring up...
for our next-generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis... SystemVerilog/Verilog RTL targeted for advanced FPGA architectures (AMD/Xilinx, Altera/Intel) meeting strict timing, power, and area...
. Job Description: Responsibilities Develop RTL for Xilinx (AMD) FPGA and/or Lattice CPLD designs Selection of appropriate parts for designs weighing..., design, synthesis and timing validation in Verilog RTL Creating IP for interface controllers, functionality...
. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies. Be able... - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs Amazon is an equal opportunity...
in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out. Responsibilities include... and Synthesizing RTL ● Timing closure through various methods and strategies;preferable in-depth experience in top-level STA...
, PE and FW. Use AI daily for RTL generation, scripting, and timing/waveform analysis. Develop specs and checklists...
functional simulation, and tools such as Siemens Questa Strong knowledge of good Verilog RTL coding practices Scripting... with Siemens’ UVM Framework Experience in emulation Experience in RTL design Familiarity with video and display systems, MIPI...
coverage closure and provide to verification signoff. Debug complex RTL and verification issues and work closely...
across the full design lifecycle, including proposals, requirements definition, RTL development, simulation, synthesis, place...
equipment is a plus. Python scripting and data-analysis experience. Exposure to embedded systems, firmware, FPGA/RTL...