Senior Digital Design Engineer

at different stages – RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence... catalog of digital IPs to enable ease of information sharing to customers across different BUs Develop User Guides for RTL...

Lugar: Wilmington, MA | 15/01/2025 19:01:14 PM | Salario: S/. No Especificado | Empresa: Analog Devices

Digital Design Engineer

Design Engineer for production silicon shipped in volume Experience in digital design µArchitecture, RTL coding...

Lugar: USA | 15/01/2025 18:01:14 PM | Salario: S/. No Especificado | Empresa: Meta

Senior ASIC Design Engineer

. Your Impact Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL... with RTL modification. Preferred Qualifications Master's degree in Electrical or Computer engineering and 4+ years...

Lugar: San Jose, CA | 15/01/2025 18:01:41 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Senior System Engineer

, logic analyzers, and lab power supplies. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands...

Lugar: Arlington, VA | 15/01/2025 03:01:15 AM | Salario: S/. No Especificado | Empresa: Leidos

ASIC Timing Engineer, Staff

signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC...

Lugar: San Diego, CA | 15/01/2025 03:01:43 AM | Salario: S/. No Especificado | Empresa: Qualcomm

SoC Chiplet Design Lead

to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...

Lugar: Austin, TX | 15/01/2025 01:01:29 AM | Salario: S/. No Especificado | Empresa: SkillTorch