Senior Physical Design Engineer
augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...
augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...
design center (ODC) or staff augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification.../block-level test benches, executing verification plans, analysis/debugging RTL, and gate-level emulation failures...
augmentation. Services offered by Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation...
to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...
failures to determine the root cause;work with RTL and firmware engineers to resolve design defects and correct test issues.../AI processor knowledge. Proficient in debugging firmware and RTL code using simulation tools. Proficient in developing and using...
to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies... from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC...
with sufficient coverage. Drive tools to realize their best performance. Debug RTL to identify causes of failure scenarios...
methods. Familiar with entire RTL2GDS flow (RTL sim (VCS), equivalence, synthesis, P&R, intent checking...
, mixed-signal RTL+spice, s-parameters, etc. Familiarity/experience with industry -standard design and EDA tools (Cadence...
-architecture specifications. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support...