ASIC Design Engineer This role focuses on front-end RTL design for advanced image and video processing SoCs, working.... Responsibilities Design and implement Verilog and SystemVerilog blocks for an image and video processing SoC. Work on front-end RTL...
), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL.... Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA...
meter. Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low... covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design...
, including graph-level and system-level optimizations Improve end-to-end compilation flow from C/C++ (and beyond) to RTL...
development across the full-lifecycle from RTL design, verification, synthesis, timing analysis, and bring up/validation...
of processor technology to define CPU Architecture and collaborate with RTL design, Verification and Post-Silicon teams to make AMD... performance simulator development on features that have more detailed specifications. RTL model vs performance simulator model...
, techniques, and methodology 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog...
(RTL and custom), verifying, and integrating FPGA/ACAP sub-blocks Coordinating activities between different design groups...
candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems... micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers...
(PMIC and PDN) Digital design at RTL, gate-level and transistor level Modeling of SoC traffic patterns Automation...