Senior Logic Design Engineer, Cache Coherent Interconnects

, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting... performance and low power RTL, Synthesis and Timing closure, and design documentation. Collaborate with our verification team...

Lugar: Santa Clara, CA | 31/10/2026 21:10:36 PM | Salario: S/. No Especificado | Empresa: Nvidia

Principal Digital IC Design Engineer

’s components. RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.... - Optimize RTL code for area, power, and performance. - Implement and verify complex digital blocks. Constraint Development...

Lugar: Minneapolis, MN | 31/10/2026 21:10:24 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group

ASIC Design Engineer

to the complete ASIC design cycle — from RTL to GDSII and silicon bring-up. Interface with customers and internal...

Lugar: Fort Collins, CO | 31/10/2026 20:10:55 PM | Salario: S/. $61900 - 99000 per year | Empresa: Broadcom

Software R&D Engineer, RTL Optimization Tools

with particular interest in strategies and algorithms for large scale RTL quality, timing, and power optimization. Such optimization... usually includes a mix of graph-based algorithms, AI, and feedback from RTL designers, so having experience relevant...

Lugar: Santa Clara, CA | 31/10/2026 20:10:48 PM | Salario: S/. No Especificado | Empresa: Nvidia

Principal ASIC/SoC Architect & Design Engineer

’s components. RTL Design and Synthesis: - Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.... - Optimize RTL code for area, power, and performance. - Implement and verify complex digital blocks. Constraint Development...

Lugar: Minneapolis, MN | 31/10/2026 20:10:45 PM | Salario: S/. No Especificado | Empresa: Chelsea Search Group