aligned with protocol and hardware standards. Partner with RTL, validation, and product teams to ensure timely..., participate in performance simulation and benchmarking, and debug issues across models, RTL, and IP. Qualifications Bachelor...
with 10 years of experience in advanced technology nodes (7nm and below). Expert in RTL-to-GDSII design flows, low-power.../AI techniques for data-driven power estimation and reduction. Proven ability to collaborate with RTL design teams to drive...
Lugar:
USA | 11/04/2026 17:04:23 PM | Salario: S/. No Especificado | Empresa:
Cloudious. Solid grounding in RTL design flows, IP integration, and timing closure concepts. Ability to create software-driven test...
. RTL Verification & Debug Run simulations, triage failures, and work closely with RTL designers to debug issues. Review... micro‑architecture and RTL to identify corner cases and test gaps. Create checkers, scoreboards, assertions, and coverage...
of RTL design and optimization while working closely with design, verification, and manufacturing partners...: Design and optimize RTL for DRAM-related digital circuits and block-level designs Perform STA and drive timing closure...
Lugar:
Boise, ID | 11/04/2026 00:04:57 AM | Salario: S/. No Especificado | Empresa:
Micron, verify, and validate RTL blocks and system-level features used in next-generation FPGA products. Key Responsibilities...) Assist in debugging RTL and verification failures, working closely with design engineers Verify common communication...
Lugar:
San Jose, CA | 11/04/2026 00:04:26 AM | Salario: S/. $95000 - 100000 per year | Empresa:
Altera with RTL and optical team. Ensures all operating policies and procedures are followed at the highest level to include...
you deliver directly accelerates the path from RTL to silicon. About the team At Annapurna Labs, your infrastructure work...
Lugar:
Austin, TX | 10/04/2026 23:04:56 PM | Salario: S/. No Especificado | Empresa:
Amazon:** 25528 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar:
Natchez, MS | 10/04/2026 23:04:38 PM | Salario: S/. $45000 - 50000 per year | Empresa:
Acosta, verify, and validate RTL blocks and system-level features used in next-generation FPGA products. Key Responsibilities... (VCS, QuestaSim, ModelSim) Assist in debugging RTL and verification failures, working closely with design engineers...
Lugar:
San Jose, CA | 10/04/2026 23:04:29 PM | Salario: S/. $100000 - 105000 per year | Empresa:
Altera