Lead ASIC DFT (Design-for-Test) Engineer - Remote

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: USA | 25/06/2026 17:06:12 PM | Salario: S/. No Especificado | Empresa: Saransh Inc

DFT Engineers

validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals...

Lugar: Santa Clara, CA | 25/06/2026 17:06:58 PM | Salario: S/. No Especificado | Empresa: VDart

DFT Engineers

validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals...

Lugar: Santa Clara, CA | 25/06/2026 17:06:04 PM | Salario: S/. No Especificado | Empresa: Ztek Consulting

Lead ASIC DFT Engineer

, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and silicon validation.... Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality. Act as a technical...

Lugar: San Jose, CA | 25/06/2026 17:06:28 PM | Salario: S/. No Especificado | Empresa: Accord Technologies Inc.

Director, Physical Design & CAD Methodology (ASIC/SoC)

features to optimize PPA and shorten turnaround times. Partner closely with RTL Design, DFT (Design for Test), Architecture... geometries (7nm, 5nm, 3nm and 2nm) Experience with full RTL-to-GDSII design flows Experience with physical verification (DRC...

Lugar: San Jose, CA | 25/06/2026 17:06:42 PM | Salario: S/. No Especificado | Empresa: Cisco Systems