ASIC Design Engineer, Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... and waveform debug experience. Experience resolving setup and hold timing violations with RTL modification. Experience developing...

Lugar: San Jose, CA | 16/01/2025 18:01:34 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

ASIC Design Engineer, Senior Technical Leader

and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help... with RTL modification. Experience developing micro-architecture solutions and RTL implementation. Preferred Qualifications...

Lugar: San Jose, CA | 16/01/2025 18:01:48 PM | Salario: S/. No Especificado | Empresa: Cisco Systems

Sr. Physical Design Engineer

as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect.... In-Depth Knowledge of design flow from RTL to GDSII. Good knowledge of EM-IR sign-off requirements. Experience in using EDA...

Lugar: Palo Alto, CA | 16/01/2025 18:01:50 PM | Salario: S/. $66.34 per hour | Empresa: Belcan

SOC Verification Engineer

team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration..., you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture...

Lugar: Sunnyvale, CA | 16/01/2025 18:01:43 PM | Salario: S/. No Especificado | Empresa: Apple

Marketing Manager, Children's, DK (Hybrid)

Marketing Manager, Children's, DK (Hybrid) DK is seeking a creative, organized, and dynamic Children's Marketing Manager to oversee title-specific marketing campaigns for both frontlist and backlist titles, with a focus on the children's ...

Lugar: New York City, NY | 16/01/2025 18:01:15 PM | Salario: S/. $70000 - 73500 per year | Empresa: RTL

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: Arlington, VA | 16/01/2025 03:01:08 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: El Cajon, CA | 16/01/2025 03:01:00 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: Chula Vista, CA | 16/01/2025 03:01:32 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior System Engineer

. Familiarity with SoC design flow to include RTL, DFT, PD, Verification Hands-on development of low-level embedded system...

Lugar: La Jolla, CA | 16/01/2025 03:01:01 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos