ASIC Engineer

chips. You will also design RTL as per the architecture specs. Your collaboration with architects, and software teams... Specification and test plan reviews Implementing RTL designs Building test cases, scripts, reference models and testbenches...

Lugar: San Jose, CA | 26/01/2026 18:01:53 PM | Salario: S/. $135800 - 193400 per year | Empresa: Splunk

Hardware FPGA Design Engineer - Acacia (Hybrid)

Contribute to FPGA Emulation of ASIC Blocks Contribute to our custom ASIC RTL code Minimum Qualifications: Bachelors +8... with minimum 5+ years of FPGA design and verification experience Experience in Verilog RTL coding and synthesis for FPGAs...

Lugar: Maynard, MA | 26/01/2026 18:01:26 PM | Salario: S/. No Especificado | Empresa: Splunk

ASIC Engineering Technical Leader

. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements...

Lugar: San Jose, CA | 26/01/2026 18:01:39 PM | Salario: S/. No Especificado | Empresa: Splunk

Neuromorphic Silicon Design Engineer

, from architecture modeling to RTL design to asynchronous circuits across processing cores, memory, networking, and interfaces... interfaces. • Enter RTL and asynchronous design (CSP/CAST) optimized for synthesis and place-and-route closure. • Work...

Lugar: Hillsboro, OR | 26/01/2026 00:01:49 AM | Salario: S/. No Especificado | Empresa: Intel

Senior Analog Design Engineer

), analog circuit simulation (Spectre/ADE), and digital RTL design (System Verilog). · Knowledge of mixed mode simulation...

Lugar: Santa Clara, CA | 25/01/2026 18:01:20 PM | Salario: S/. No Especificado | Empresa: Adecco