Digital ASIC Design Engineer

for RTL Design, flows and methodology for high performance ASICs in sub-4nm process for mobile, automotive, compute, AI and XR... field RTL design experience with Verilog/System Verilog or VHDL Proficiency in any automation/scripting language...

Lugar: San Diego, CA | 09/04/2026 23:04:44 PM | Salario: S/. $98500 - 147700 per year | Empresa: Qualcomm

Senior CAD Engineer, ASIC Development Infrastructure, RTL Design

and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing... Engineering or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs...

Lugar: Boise, ID | 09/04/2026 22:04:43 PM | Salario: S/. No Especificado | Empresa: Amazon

Staff Engineer

\. RTL or gate level verification 6\. Modeling, Performance Analysis, Timing Analysis, Logic schematic Analysis 7...

Lugar: Richardson, TX | 09/04/2026 21:04:53 PM | Salario: S/. No Especificado | Empresa: Micron

Physical Design Engineer, Annapurna Labs

right trade-offs. Key job responsibilities Work with RTL/logic designers to drive architectural feasibility studies... with other physical design engineers as well as with the RTL/Arch. teams About the team Our team is dedicated to supporting new members...

Lugar: Cupertino, CA | 09/04/2026 20:04:25 PM | Salario: S/. No Especificado | Empresa: Amazon