ASIC Design Engineer - Memory Cache Controller

, and power consumption along with the performance analysis team. Develop/debug RTL design of different sections of the cache... Development of memory systems. Experience in RTL/micro-architecture definition. Experience in PPA (performance/power/area...

Lugar: Santa Clara, CA | 08/01/2025 03:01:07 AM | Salario: S/. No Especificado | Empresa: Apple

RTL Design Engineer

hardworking RTL Design Engineer. Are you early in your journey towards a chip design career and wish to challenge... DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified...

Lugar: Waltham, MA | 08/01/2025 03:01:29 AM | Salario: S/. No Especificado | Empresa: Apple

FPGA Design Engineer

Responsibilities Drive RTL development and testing for FPGA targets/platforms to support rapid prototyping Partner with Design... (RTL, Simulation, Implementation, Hands on bring-up and debug) Experience with commercial HDL simulators (Modelsim...

Lugar: Sunnyvale, CA | 08/01/2025 02:01:40 AM | Salario: S/. No Especificado | Empresa: Meta

SoC Design Verification Engineer - x86 Core

verification tests. Debug test failures to determine the root cause;work with RTL and firmware engineers to resolve design... knowledge (x86 Core). Proficient in debugging firmware and RTL code using simulation tools. Proficient in developing...

Lugar: Boxborough, MA | 08/01/2025 01:01:25 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

ASIC Design Engineer

analysis on suggested architecture(s) and algorithm(s) Perform RTL design and logic implementation of agreed architecture...

Lugar: Cupertino, CA | 08/01/2025 01:01:05 AM | Salario: S/. No Especificado | Empresa: Apple

ASIC Design Engineer - Pixel IP

microarchitecture specifications. - RTL design - Development and refinement of RTL implementations to meet functional, power...

Lugar: Cupertino, CA | 08/01/2025 00:01:21 AM | Salario: S/. No Especificado | Empresa: Apple