with architecture, u-arch, RTL, performance modeling, firmware, and software teams to define and validate performance KPIs. Ensure... to debug performance outliers through Performance Monitoring Counters (PMC). Drive correlation between RTL and performance...
related field, or equivalent practical experience At least 2 years of hands-on experience designing RTL digital logic using...
), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL.... Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA...
infrastructure Correlate silicon measurements against RTL simulation and emulation predictions A day in the life Your primary...
. What You Will Do: Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration... date U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance RTL coding and simulation in VHDL...
, decomposition, and traceability. Develop RTL design code and simulation in VHDL, Verilog, and/or System Verilog. Develop Hardware... of experience. Experience writing RTL and test benches using VHDL, UVM, Verilog, or SystemVerilog. Experience with Linux (or Unix...
leadership and communication — Partner routinely with Program/Project Management, Physical Design, Package / SI, RTL/Design...
. Experience developing complex ASICs including defining micro-architecture, implementing RTL in Verilog/System Verilog...
collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams About the team Why AWS... from RTL-to-GDSII - Understanding of other sign-off activities (ir/em, physical verification, DFT) Preferred Qualifications...
through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab... -Develop and optimize RTL code for high-performance, resource-efficient designs -Perform timing analysis, synthesis, place...