Silicon Technical Lead

, including RTL, Physical Design (PD), Design Verification (DV), and post-silicon bringup. Define and drive the end-to-end... (e.g., RTL, PD, DV) and strong familiarity with the entire ASIC flow. Experience with managing silicon vendors...

Lugar: Mountain View, CA | 09/01/2026 03:01:29 AM | Salario: S/. No Especificado | Empresa: DeepMind

ASIC Design Verification Engineer

and random verification tests. Debug test failures to determine the root cause;work with RTL engineers to resolve design.... Proficient in debugging RTL code using simulation tools. Proficient in using UVM testbenches and working in Linux and Windows...

Lugar: Boxborough, MA | 09/01/2026 02:01:03 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Principal CAD Engineer

communication skills Ability to run the following tasks is a plus: RTL to gates, and gates-to-gates equivalence checking Chip...

Lugar: Santa Clara, CA | 09/01/2026 01:01:01 AM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell

Senior Staff GPU Design Verification Engineer- Power

methodology to improve the verification flows. System level RTL simulation & design verification. Support SoC DV... verification components/UVCs, testbench for RTL verification 5+ years of hands on testbench bringup, integrating third party VIPs...

Lugar: San Diego, CA | 09/01/2026 01:01:29 AM | Salario: S/. No Especificado | Empresa: Qualcomm

EDA Methodology Architect

, with expertise in key stages such as RTL, DFT, synthesis, placement, optimization, CTS, routing, and signoff. Creativity and self..., RTL, DFT, synthesis, physical design, power, signoff, and CAD/methodology teams as a key technical leader and bridge...

Lugar: Santa Clara, CA | 09/01/2026 00:01:04 AM | Salario: S/. No Especificado | Empresa: Nvidia

Low Power Design Verification Engineer

and random verification tests Debug test failures to determine the root cause;work with RTL and firmware engineers to resolve...., UPF, power domains, multi-voltage) NPU/AI processor knowledge Proficient in debugging firmware and RTL code using...

Lugar: Boxborough, MA | 08/01/2026 21:01:33 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices

Senior ASIC Physical Design Engineer, Netlisting

. Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools. Deep understanding... of hardware architecture and hands-on skills in RTL/logic design for timing closure. Experience in clock-domain-crossing...

Lugar: Santa Clara, CA | 08/01/2026 21:01:43 PM | Salario: S/. No Especificado | Empresa: Nvidia
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