Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design...
Senior Engineer - Design for Test (DFT)
test plans and engage closely with verification engineers to perform waveform reviews. Ensure RTL quality pre-DFT to ensure... the RTL is good for DFT insertion and coverage. Hold a primary role in enabling silicon by working directly with test...
Lugar: Hillsboro, OR | 31/12/2025 02:12:29 AM | Salario: S/. No Especificado | Empresa: Microsoft
CPU Micro-Architect RTL Engineer
microarchitecture and RTL design, with knowledge in one or more of the following areas: Processor pipelines Out-of-order execution...-V architecture You will own microarchitecture and RTL development, including low-power optimizations, performance exploration...
Lugar: Austin, TX | 31/12/2025 00:12:17 AM | Salario: S/. No Especificado | Empresa: Qualcomm
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
Lugar: Irvine, CA | 30/12/2025 22:12:06 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom
Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration - Annapurna Labs
efficient RTL to achieve design targets and specifications. - Analyze design, microarchitecture or architecture to make trade...-offs based on features, power, performance or area requirements. - Develop micro-architecture, implement SystemVerilog RTL...
Lugar: Austin, TX | 30/12/2025 21:12:10 PM | Salario: S/. No Especificado | Empresa: Amazon
R&D IC Design Engineer
, RTL/gate level simulations & silicon debugging scripting for various IC design tasks such as STA, equivalency checks... and problem solving skills as well as hands-on lab debugging experiences Good knowledge of RTL simulation and synthesis...
Lugar: Irvine, CA | 30/12/2025 20:12:30 PM | Salario: S/. No Especificado | Empresa: Broadcom
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design for test...
Lugar: Irvine, CA | 30/12/2025 19:12:23 PM | Salario: S/. No Especificado | Empresa: Broadcom
R&D IC Design Engineer
design document, timing constraint file ï‚· RTL coding, Lint checks, CDC, Synthesis, Equivalency checking, STA, RTL/gate... experiences ï‚· Good knowledge of RTL simulation and synthesis. ï‚· In-depth knowledge for design for low power and design...
Lugar: Irvine, CA | 30/12/2025 19:12:02 PM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom
Physical Design Engineer II (Silicon Engineering)
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
Wireless Sales Manager - Longview, TX
:** 18883 **Employer Description:** PREM\_RTL\_SERV\_EMP\_DESC...
Lugar: Longview, TX | 30/12/2025 18:12:42 PM | Salario: S/. $45000 - 50000 per year | Empresa: Acosta