(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms - RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 19/12/2025 19:12:43 PM | Salario: S/. $150000 - 190000 per year | Empresa: SES S.A.

(Senior) Engineer, DSP Systems Engineering, meoSphere

into implementable DSP blocks for ASIC design, collaborating with RTL and physical design teams to define fixed-point accuracy... algorithms — RTL handoff, verification, and bit-accurate modelling. Experience in lab-based silicon bring-up, calibration...

Lugar: Long Beach, CA | 19/12/2025 18:12:35 PM | Salario: S/. $150000 - 190000 per year | Empresa: SES

Financial Operations Analyst

. has a track record of originating $1.5+ billion of residential transition loans (RTL) to real estate investors through its... vehicle for current and future RTL originations. About the Role: This position supports the Capital Markets team...

Lugar: Texas | 19/12/2025 18:12:58 PM | Salario: S/. No Especificado | Empresa: Vontive

Senior Digital Design Engineer

logic required to implement new products in a wide range of application spaces RTL digital design and problem solving... such as linear regulators, DC-DC converters, data converters, and mixed signal processing functions. RTL design for synchronous...

Lugar: Chandler, AZ | 19/12/2025 03:12:41 AM | Salario: S/. No Especificado | Empresa: Analog Devices

Design/DSP/Verification Intern - Bachelor's Degree

timing diagrams Implement block level design using RTL Coding guidelines Run Synthesis and Lint flow to ensure timing... simulation or emulation platforms Hands-on experience with RTL integration and bring-up system Experience with debugging...

Lugar: Santa Clara, CA | 19/12/2025 01:12:22 AM | Salario: S/. $27 - 53 per hour | Empresa: Marvell

Senior/Principal ASIC Digital Design Engineer

, recurring cost and security functions. Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages... methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification...

Lugar: Boise, ID | 19/12/2025 00:12:53 AM | Salario: S/. No Especificado | Empresa: Idaho Scientific