Camera Design Engineer

Image Signal Processing algorithms Own and deliver core level IP RTL design Run synthesis, review results to ensure..., Engineering, or related field. Ideal candidate to have 3+ years of industry exp. in: Verilog or VHDL RTL design Design...

Lugar: San Diego, CA | 12/12/2025 00:12:08 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Senior ASIC Design Engineer, Hardware Compute Group

across multiple disciplines Develop detailed design specifications and documentation Perform RTL coding and synthesis Work... by them Participate in test plan and coverage reviews The ideal candidate should have experience with RTL development...

Lugar: Sunnyvale, CA | 11/12/2025 19:12:36 PM | Salario: S/. No Especificado | Empresa: Amazon

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 11/12/2025 03:12:47 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Sr. Design Engineering Architect - Front End

and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture...: Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals. RTL Development...

Lugar: Austin, TX | 11/12/2025 02:12:08 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 11/12/2025 00:12:00 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 23:12:52 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Technical Director, Digital Design and Verification

of RTL/Verilog, and familiarity with mid/back-end digital design Expertise in front-end digital including timing, synthesis... RTL and gates is desired Behavioral modeling of RF and AMS circuits for ASIC/Module level verification...

Lugar: San Diego, CA | 10/12/2025 22:12:12 PM | Salario: S/. No Especificado | Empresa: Murata