FPGA Design Verification Engineer

, System Verilog, RTL). · Write and debug test cases to verify functionality, performance, and corner cases. · Identify... functions may be required. What you need: · Strong understanding of FPGA, ASIC, RTL design principles and architectures...

Lugar: Mountain View, CA | 06/12/2025 18:12:43 PM | Salario: S/. No Especificado | Empresa: UST

Senior Staff Engineer, Physical Design

across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...

Lugar: Morrisville, NC | 06/12/2025 02:12:51 AM | Salario: S/. $125900 - 186260 per year | Empresa: Marvell

Senior Staff Engineer, Physical Design

across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...

Lugar: Santa Clara, CA | 06/12/2025 00:12:04 AM | Salario: S/. $124420 - 186400 per year | Empresa: Marvell

Bell Labs Platform&ASIC Research Intern

DSPs Advanced RTL development skills and fluent in HDL (Verilog, SystemVerilog, and VHDL) and/or HLS (High-level Synthesis... in gate or RTL-level design optimization, timing closure analysis, and/or mixed-signal circuit design About Us: Advancing...

Lugar: Murray Hill, NJ | 05/12/2025 23:12:43 PM | Salario: S/. No Especificado | Empresa: Nokia