Physical IC Design Engineer

, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out..., and Timing Closure Setup and Synthesizing RTL Timing closure through various methods and strategies;preferable in-depth...

Lugar: San Jose, CA | 11/12/2025 00:12:04 AM | Salario: S/. No Especificado | Empresa: Broadcom

Senior FPGA Development Engineer, Bespoke Solutions

for each government agency for which they perform AWS work. 10012 Key job responsibilities - Develop custom RTL and integrate... with custom hardware. You will debug RTL in simulation, synthesize and implement ensuring it meets timing and performance...

Lugar: Arlington, VA | 10/12/2025 23:12:37 PM | Salario: S/. $159200 - 215300 per year | Empresa: Amazon

Physical IC Design Engineer

Design aspects of taking RTL to silicon tape-out. Responsibilities include, but are not limited to the following...: Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL Timing closure...

Lugar: San Jose, CA | 10/12/2025 22:12:00 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom