Sr. ASIC Design Engineer (Silicon Engineering)

, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate... in RTL implementation PREFERRED SKILLS AND EXPERIENCE: Ability to solve complex problems including clock domain...

Lugar: USA | 23/12/2025 18:12:24 PM | Salario: S/. No Especificado | Empresa: SpaceX

Principal ASIC Design Engineer (Silicon Engineering)

-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis... engineering, computer engineering, or computer science 10+ years of experience in RTL implementation and/or FPGA/ASIC development...

Lugar: USA | 23/12/2025 18:12:56 PM | Salario: S/. No Especificado | Empresa: SpaceX

Director of Business Development

, with teams in Ottawa, Waterloo, and San Jose focusing on FPGA design, embedded software, ASIC RTL design and verification...

Lugar: USA | 23/12/2025 18:12:22 PM | Salario: S/. No Especificado | Empresa: Fidus Systems

Director of Business Development

, with teams in Ottawa, Waterloo, and San Jose focusing on FPGA design, embedded software, ASIC RTL design and verification...

Lugar: USA | 23/12/2025 18:12:34 PM | Salario: S/. No Especificado | Empresa: Fidus Systems

Transportation Specialist-Crawfordsville, Indiana

We use cookies to offer you the best possible website experience. Your cookie preferences will be stored in your browser's local storage. This includes cookies necessary for the website's operation. Additionally, you can freely decide and c...

Lugar: Crawfordsville, IN | 21/12/2025 03:12:44 AM | Salario: S/. No Especificado | Empresa: RTL

Senior Video Design Engineer

-architecture and RTL to meet performance, area, and power requirements Reviewing linting, synthesis, CLP, CDC, and DV coverage... and managing multiple tasks Principal duties: RTL implementation using Verilog/SystemVerilog Design optimization for power...

Lugar: San Diego, CA | 21/12/2025 03:12:09 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Senior Pre-Silicon Verification Engineer

. Finds and implements corrective measures to resolve failing tests. Collaborates with CPU architects, RTL developers.../C++ System Verilog coding and debug Experience with RTL development Knowledge of system level boot flows and power...

Lugar: Austin, TX | 21/12/2025 03:12:55 AM | Salario: S/. No Especificado | Empresa: Intel