Senior ASIC Design Engineer

Design teams to ensure RTL quality supports timing closure, power targets, and manufacturability on advanced process nodes...

Lugar: San Jose, CA | 24/12/2025 18:12:57 PM | Salario: S/. No Especificado | Empresa: Persimmons

Senior Design Engineer – AI SoC Development

constraints, and system limitations. Microarchitecture & RTL Development: Define and document microarchitecture for complex SoC... IP blocks;implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver synthesis- and timing-clean...

Lugar: Folsom, CA | 24/12/2025 18:12:10 PM | Salario: S/. No Especificado | Empresa: Intel

Director of Business Development

, with teams in Ottawa, Waterloo, and San Jose focusing on FPGA design, embedded software, ASIC RTL design and verification...

Lugar: USA | 24/12/2025 18:12:45 PM | Salario: S/. No Especificado | Empresa: Fidus Systems

Design Engineer – AI SoC Development

ideal candidate for this role. Join us to shape the future of AI hardware. What You'll Do As an RTL Design Engineer..., you'll develop logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks...

Lugar: Folsom, CA | 24/12/2025 01:12:34 AM | Salario: S/. No Especificado | Empresa: Intel

ASIC Design Verification Engineer - New College Grad 2026

related verification methodologies for the corresponding design (RTL). For this position, you should have real passion.... Strong coding skills in Python or other industry-standard scripting languages. Strong understanding of RTL design (Verilog...

Lugar: Austin, TX | 24/12/2025 00:12:05 AM | Salario: S/. $108000 - 184000 per year | Empresa: Nvidia

Sr. Manager YouTube

, and education company Bertelsmann, whose other content businesses include the entertainment company RTL Group and the trade book...

Lugar: Los Angeles, CA | 23/12/2025 23:12:21 PM | Salario: S/. $80000 - 90000 per year | Empresa: Penguin Books

Principal ASIC Design Engineer (Silicon Engineering)

-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis... engineering, computer engineering, or computer science 10+ years of experience in RTL implementation and/or FPGA/ASIC development...

Lugar: USA | 23/12/2025 18:12:59 PM | Salario: S/. No Especificado | Empresa: SpaceX