Senior FPGA Engineer

/400 Gz data rates. Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL...

Lugar: Ashburn, VA | 21/11/2025 18:11:34 PM | Salario: S/. $108900 - 150000 per year | Empresa: Curtiss-Wright

Design Verification Engineer

industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL...

Lugar: San Jose, CA | 21/11/2025 02:11:51 AM | Salario: S/. No Especificado | Empresa: Broadcom

IP Integration Engineer

. Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC...: Experience with the Cadence Virtuoso design environment Experience or coursework with RTL languages (i.e SystemVerilog, Verilog...

Lugar: Fort Collins, CO | 21/11/2025 02:11:20 AM | Salario: S/. $91000 - 146000 per year | Empresa: Broadcom

Senior SoC Power Architect

(RTL, PD, Circuit, SI, Thermal, SW, Platform, Operations, Marketing, etc...) to deliver outstanding power solutions...

Lugar: Santa Clara, CA | 21/11/2025 01:11:37 AM | Salario: S/. No Especificado | Empresa: Nvidia

Design Verification Engineer

industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL...

Lugar: San Jose, CA | 20/11/2025 21:11:20 PM | Salario: S/. No Especificado | Empresa: Broadcom

SoC Design Engineer

Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis...

Lugar: Santa Clara, CA | 20/11/2025 20:11:17 PM | Salario: S/. $110600 - 140000 per year | Empresa: OmniVision