Sr. ASIC Design Engineer (Silicon Engineering)

, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate... in RTL implementation PREFERRED SKILLS AND EXPERIENCE: Ability to solve complex problems including clock domain...

Lugar: USA | 20/11/2025 18:11:23 PM | Salario: S/. No Especificado | Empresa: SpaceX

RTL & Codesign Engineer

that accelerate innovation and enable hardware optimized specifically for AI. About the Role We're looking for a RTL Engineer.... Responsibilities Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems Contribute...

Lugar: San Francisco, CA | 20/11/2025 18:11:57 PM | Salario: S/. No Especificado | Empresa: OpenAI

React (NextJS) Lead

, Prettier) Automated testing frameworks (Jest, RTL, Cypress, Playwright) Static analysis tools Optimize build performance...

Lugar: Irving, TX | 20/11/2025 18:11:43 PM | Salario: S/. No Especificado | Empresa: InterSources

Chip Integration Engineer

successful candidate will be responsible for various key tasks in the areas of chip integration and RTL design of cutting-edge network.... 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static...

Lugar: San Jose, CA | 20/11/2025 03:11:45 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Design Verification Intern

Create a verification plan (vplan) for a selected RTL design Set up a verification testbench using System Verilog and UVM... methodologies Write checkers, assertions and coverage to verify the RTL Run simulations to verify design functionality...

Lugar: Edinburgh - Freer, TX | 20/11/2025 03:11:46 AM | Salario: S/. No Especificado | Empresa: Analog Devices

Digital Design Intern

products. This internship offers hands-on experience in RTL design, simulation, and verification using the industry standard... Responsibilities Assist in creating and updating RTL (Register Transfer Level) designs using Verilog Collaborate with analog...

Lugar: Edinburgh - Freer, TX | 20/11/2025 01:11:17 AM | Salario: S/. No Especificado | Empresa: Analog Devices

Physical Design Engineer

experience - Work closely with RTL & DFT designers - Strong TCL/Python scripting knowledge required, Perl is a plus. - Good...

Lugar: San Jose, CA | 20/11/2025 00:11:07 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

Senior ASIC Design Engineer

design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design... limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design...

Lugar: Santa Clara, CA | 19/11/2025 23:11:32 PM | Salario: S/. No Especificado | Empresa: Nvidia