HBM SoC Physical Design Engineer

logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers...) across multi-mode/multi-corner (MMMC) scenarios;partner with RTL, architecture, and STA/signoff to converge designs. Integrate...

Lugar: Folsom, CA | 24/10/2026 18:10:17 PM | Salario: S/. $103000 - 210000 per year | Empresa: Micron

Lead FPGA Design Engineer

FPGA design experience. Proficiency in the design, implementation, and simulation for RTL in SystemVerilog and/or VHDL...

Lugar: San Jose, CA | 29/10/2026 20:10:08 PM | Salario: S/. $123000 - 205000 per year | Empresa: @Orchard

Sr Engineer SoC Physical Verification, HBM

layout, computer‑aided design (CAD), register‑transfer level (RTL), product engineering, EDA, and foundry teams, including... or customization. Working knowledge of full RTL‑to‑GDS implementation flows, including place‑and‑route, extraction...

Lugar: Folsom, CA | 30/08/2026 01:08:31 AM | Salario: S/. $97000 - 205000 per year | Empresa: Micron

Senior Staff Digital Design Engineer

blocks.  Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL that meets... ASIC design, including micro‑architecture development, RTL implementation (SystemVerilog preferred), and integration...

Lugar: Irvine, CA | 19/09/2026 01:09:06 AM | Salario: S/. $135900 - 201130 per year | Empresa: Marvell

Senior VHDL RTL Digital Logic Engineer

Engineer with a focus in VHDL Register-Transfer Level (RTL) Digital Logic design for our R&D Communications product group..., and other communication products. As a Senior VHDL RTL Digital Logic Engineer, a typical day may include the following: Serving...

Lugar: Pullman, WA | 28/08/2026 00:08:25 AM | Salario: S/. $136000 - 201000 per year | Empresa: Schweitzer Engineering Laboratories

Lead FPGA Engineer

standards for manufacturing, service as required Preferred Qualifications Familiar with FPGA RTL code and related high speed... and constraints at the PCB/FPGA interface. Experience with Xilinx/Altera FPGA RTL design using SystemVerilog/Verilog/VHDL, FPGA...

Lugar: Milpitas, CA | 07/08/2026 23:08:36 PM | Salario: S/. $117800 - 200300 per year | Empresa: KLA Corporation

Litigation Legal Paralegal

in our next-generation AI processor. You’ll collaborate with experts across architecture, RTL design, physical design, firmware...

Lugar: Houston, TX | 02/11/2026 01:11:49 AM | Salario: S/. $150000 - 200000 per year

Litigation Legal Paralegal

in our next-generation AI processor. You’ll collaborate with experts across architecture, RTL design, physical design, firmware...

Lugar: Dallas, TX | 02/11/2026 01:11:49 AM | Salario: S/. $150000 - 200000 per year