flows Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place... RTL, verification, and CAD, to ensure cohesive and optimized design execution. Mentor and coach senior and junior...
Engineer within Custom Silicon Engineering (CCS), you will be part of a high-performance RTL team responsible for architecting... and implementing advanced SoC designs. CCS serves as the core execution engine for customer-driven silicon programs, delivering RTL, DV...
Engineer, you will be at the forefront of innovation—driving micro-architecture and RTL development while spearheading HW/SW... and optimizing Verilog RTL, with expertise in Spyglass for thorough LINT and Clock Domain Crossing (CDC) checks to ensure flawless...
for each government agency for which they perform AWS work. 10012 Key job responsibilities - Develop custom RTL and integrate... with custom hardware. You will debug RTL in simulation, synthesize and implement ensuring it meets timing and performance...
Lugar:
Arlington, VA | 10/12/2025 23:12:25 PM | Salario: S/. $159200 - 215300 per year | Empresa:
Amazon responsibility of the digital architecture, design, Verilog RTL coding, implementation, and verification of next generation wireless...
Lugar:
San Diego, CA | 21/11/2025 02:11:34 AM | Salario: S/. $152566 - 210000 per year | Empresa:
Qualcomm as a first level manager of an engineering team. Extensive experience coding RTL (Verilog preferred). Extensive experience...
QCluster RTL will be used as the reference for performance modeling, along with behavioral models for a RISC-V core and a PCIe... Controller. Responsibilities: Implement SystemC-based timing models for Qcore and Qcluster units derived from RTL Integrate...
with a multidisciplinary team of mechanical, thermal, software, RTL, RF, GNC, and manufacturing engineers to solve challenging problems...
Lugar:
California | 01/10/2025 19:10:07 PM | Salario: S/. $140000 - 200000 per year | Empresa:
Astrani. Collaborate with RTL designers to influence future NPU and FPGA architecture from an ML software perspective. Lead R&D on model... of computer architecture, digital logic, and the role of RTL (Verilog/VHDL) in the hardware design lifecycle. Proven experience...
Lugar:
San Jose, CA | 19/11/2025 18:11:14 PM | Salario: S/. $80000 - 200000 per year | Empresa:
Axiado) supports for multi-die design. DFT Design and Verification fundamentals: Ability to read and understand RTL code. A solid...
Lugar:
Fremont, CA | 12/12/2025 02:12:06 AM | Salario: S/. $109800 - 197700 per year | Empresa:
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