Senior Video Design Engineer

-architecture and RTL to meet performance, area, and power requirements Reviewing linting, synthesis, CLP, CDC, and DV coverage... and managing multiple tasks Principal duties: RTL implementation using Verilog/SystemVerilog Design optimization for power...

Lugar: San Diego, CA | 20/12/2025 19:12:45 PM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Camera Design Engineer

Image Signal Processing algorithms Own and deliver core level IP RTL design Run synthesis, review results to ensure..., Engineering, or related field. Ideal candidate to have 3+ years of industry exp. in: Verilog or VHDL RTL design Design...

Lugar: San Diego, CA | 12/12/2025 02:12:15 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

CPU Power Analysis Engineer

characterization of various CPU benchmarks using tools like PTPX and Joules. Work closely with RTL design, Synthesis, and physical... communication skills. Preferred Qualifications Experience with low power implementation techniques in RTL, Synthesis or Physical...

Lugar: Austin, TX | 10/12/2025 01:12:50 AM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

CPU Physical Design Timing Engineer (Austin, TX)

Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive... environment. Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus Minimum Qualifications...

Lugar: Austin, TX | 21/11/2025 21:11:06 PM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Physical Design Engineer

closely with RTL & DFT designers Strong TCL/Python scripting knowledge required, Perl is a plus. Good debug skill...

Lugar: California | 26/11/2025 18:11:16 PM | Salario: S/. $130000 - 180000 per year | Empresa: Quest Global

RTL Design & Verification/ Power Engineer

Jobs Job Description Apply now Start Please wait... Job Title: RTL Design & Verification/ Power Engineer City: Mountain View State/Province.... For additional information, visit us at www.wipro.com. Job Description: RTL Design & Verification/ Power Engineer RTL Design...

Lugar: Mountain View, CA | 30/01/2026 01:01:47 AM | Salario: S/. $100000 - 180000 per year | Empresa: Wipro

Principal/ Senior Principal Digital ASIC Circuit Design Engineer

circuits. Must be proficient in Verilog, System Verilog or VHDL RTL coding, write functional test benches and have a thorough... is a plus. Must have strong written and oral communication skills. Responsibilities: Circuit behavioral coding in Verilog, System Verilog or VHDL RTL...

Lugar: USA | 26/11/2025 18:11:18 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman