ASIC & FPGA Design Engineer Sr - E3

, software, and hardware groups to transform MATLAB/Simulink models into efficient, synthesizable RTL and integrate that RTL onto... synthesis (Vitis HLS) and RTL code (VHDL/Verilog/SystemVerilog). Writing, simulating, and verifying RTL and HLS implementations...

Lugar: Orlando, FL | 10/09/2026 17:09:41 PM | Salario: S/. $98100 - 182100 per year | Empresa: Lockheed Martin

FPGA Designer

, MR, and Ultrasound platforms. Familiarity with power electronics and/or ASIC RTL design is a strong... platforms. Familiarity with power electronics and/or ASIC RTL design is a strong plus. Job Description Roles...

Lugar: Niskayuna, NY | 23/10/2026 19:10:23 PM | Salario: S/. $120000 - 180000 per year | Empresa: GE HealthCare

Memory System Designer and Place and Route Engineer

and design memory subsystems Implement RTL of subsystem designs Place and route (physical design) Design closure: timing, DRC... RTL code Place and route expertise Proficient in running STA, DRC, EM/IR tools, and attaining design closure Ability...

Lugar: USA | 08/10/2026 02:10:34 AM | Salario: S/. $109700 - 175500 per year | Empresa: Broadcom

DSP System Architect

with RTL simulations Define and document chip requirements, architecture, verification and lab test plan Lab testing...

Lugar: Irvine, CA | 12/09/2026 23:09:37 PM | Salario: S/. $109700 - 175500 per year | Empresa: Broadcom