Senior ASIC & FPGA Design Engineer
will include: Defining architecture and design specifications for programmable logic components, developing and documenting RTL...
will include: Defining architecture and design specifications for programmable logic components, developing and documenting RTL...
, software, and hardware groups to transform MATLAB/Simulink models into efficient, synthesizable RTL and integrate that RTL onto...
, software, and hardware groups to transform MATLAB/Simulink models into efficient, synthesizable RTL and integrate that RTL onto... synthesis (Vitis HLS) and RTL code (VHDL/Verilog/SystemVerilog). Writing, simulating, and verifying RTL and HLS implementations...
, MR, and Ultrasound platforms. Familiarity with power electronics and/or ASIC RTL design is a strong... platforms. Familiarity with power electronics and/or ASIC RTL design is a strong plus. Job Description Roles...
design concepts, RTL, verification, and embedded firmware. Experience building AI assisted engineering tools, automation...
and design memory subsystems Implement RTL of subsystem designs Place and route (physical design) Design closure: timing, DRC... RTL code Place and route expertise Proficient in running STA, DRC, EM/IR tools, and attaining design closure Ability...
with RTL simulations Define and document chip requirements, architecture, verification and lab test plan Lab testing...
+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL PREFERRED SKILLS AND EXPERIENCE: ASIC/FPGA...
, develop timing, power and area design targets, and explore RTL/design tradeoffs Resolve design/timing/congestion and flow...
of the Starlink network. RESPONSIBILITIES: Responsible for evaluating design readiness for scan insertion through RTL...