ASIC Digital Design Engineer
and simulation Digital Synthesis and RTL code development, implementation, and verification Additional Skills...
and simulation Digital Synthesis and RTL code development, implementation, and verification Additional Skills...
-functional teams to deliver industry-leading solutions. Key Responsibilities RTL Design & Microarchitecture Develop... synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management. Design high...
will have hands-on experience in RTL-to-GDSII flow, with a strong focus on Floor-planning, Clock Tree Synthesis, Place-n-Route (PnR... and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...
required, contribute to modeling or RTL design of components using Verilo Minimum Qualifications: Master’s degree in Computer...) neural network blocks, and digital NPUs. Proven ASIC design experience, encompassing high-speed and low-power RTL...
. Deep expertise in digital signal processing, RTL design, and digital architecture. Strong knowledge of: Firmware...
environment, we want you on our team. Key Responsibilities: Design and implement advanced FPGA modules, including RTL coding... Engineering, or a related technical field. 4–6 years of industry experience in FPGA development, including RTL coding in System...
, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams... micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing...
across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...
of the complete IC design flow, from front-end design (RTL, synthesis, simulation) to back-end physical implementation (place...
and closure on complex partitions. Develop and implement timing closure and logical ECO’s. Interface with the RTL design team...