Staff Logic Design Engineer

-functional teams to deliver industry-leading solutions. Key Responsibilities RTL Design & Microarchitecture Develop... synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and buffer management. Design high...

Lugar: Milpitas, CA | 18/11/2025 20:11:46 PM | Salario: S/. $141900 - 189200 per year | Empresa: Teledyne Technologies

HW SOC/ASIC Physical Design Engineer, Staff/Sr Staff

will have hands-on experience in RTL-to-GDSII flow, with a strong focus on Floor-planning, Clock Tree Synthesis, Place-n-Route (PnR... and modes using static timing analysis (STA) tools (e.g., PrimeTime). Collaborate with RTL designers to resolve timing...

Lugar: Boulder, CO | 06/12/2025 03:12:01 AM | Salario: S/. $126000 - 189000 per year | Empresa: Qualcomm

Staff Edge AI SOC System Architect

required, contribute to modeling or RTL design of components using Verilo Minimum Qualifications: Master’s degree in Computer...) neural network blocks, and digital NPUs. Proven ASIC design experience, encompassing high-speed and low-power RTL...

Lugar: Boston, MA | 18/11/2025 21:11:24 PM | Salario: S/. $125250 - 187875 per year | Empresa: Analog Devices

FPGA Engineer III

environment, we want you on our team. Key Responsibilities: Design and implement advanced FPGA modules, including RTL coding... Engineering, or a related technical field. 4–6 years of industry experience in FPGA development, including RTL coding in System...

Lugar: Spokane, WA | 01/10/2025 02:10:05 AM | Salario: S/. $124800 - 187200 per year | Empresa: F5

Sr. Staff Verification Design Engineer

, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams... micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing...

Lugar: Santa Clara, CA | 13/12/2025 01:12:57 AM | Salario: S/. $124420 - 186400 per year | Empresa: Marvell

Senior Staff Engineer, Physical Design

across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner Implement... verification) using industry standard EDA tools Work with RTL design teams to drive assembly and design closure. Provide...

Lugar: Santa Clara, CA | 05/12/2025 20:12:39 PM | Salario: S/. $124420 - 186400 per year | Empresa: Marvell